Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using special procedures for growth of gate oxide at various trench corners.

Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Field effect transistor and method of its manufacture

An image-forming device has a plurality of cylindrical image-carrying members, and an optical scanning unit. The plurality of cylindrical image-carrying members is provided in a main casing for rotating about respective rotational axes. The rotational axes are parallel to one another and juxtaposed in a single direction. The optical scanning unit is provided in the main casing and has a plurality of laser generators, a single rotatable polygon mirror, a plurality of mirrors, and a plurality of lenses. The plurality of laser generators is provided one-to-one relationship to the plurality of image-carrying members to emit respective laser beams. The single rotatable polygon mirror deflects the respective laser beams to scan the respective image-carrying members therewith. The plurality of mirrors is provided one-to-one relationship to the plurality of image-carrying members to guide the respective laser beams along respective optical paths to the respective image-carrying members. The plurality of lenses is provided one-to-one relationship to the plurality of image-carrying members and provided in the respective optical paths and between the respective mirrors and the respective image-carrying members. Distances from the respective mirrors to the respective image-carrying members being equal to one another.

Image-forming device

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

A semiconductor device wherein an avalanche withstand of power MISFET is improved without enlarging cell pitch In the semiconductor device, impurity ions having a p-type conduction, eg B ions, are introduced from a bottom of a contact hole to form a p-type semiconductive region that is provided below a p+-type semiconductive region and in contact with the p+-type semiconductive region and an n--type single crystal silicon layer and that has an impurity concentration lower than the p+-type semiconductive region An n-type semiconductive region is formed in the n--type single crystal silicon layer provided below the p-type semiconductive region as being in contact with the p-type semiconductive region and has an impurity concentration lower than the n--type single crystal silicon layer

Semiconductor device and a method of manufacturing the same

In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.

Insulated gate field effect transistor with source field shield extending over multiple region channel

An insulated-gate semiconductor device wherein a first region is formed in the surface of a semiconductor substrate, the first region having a conductivity type opposite to that of the substrate, two insulated-gate FET's are formed within the first region, the drain of the first insulated-gate FET and that of the second insulated-gate FET are made common, the drains are electrically connected to the first region, and the gate of the first insulated-gate FET and the source of the second insulated-gate FET, and the gate of the second insulated-gate FET and the source of the first insulated-gate FET are respectively connected, thereby to prevent the occurrence of a negative resistance.

Insulated gate semiconductor device

An insulated gate type field effect transistor for high power which has a low conductivity region surrounding a drain region and an offset gate region having a further lower conductivity adjoined thereto, wherein the length and impurity concentration are designed according to the electric characteristics of the transistor. A combination of P channel and N channel type transistors having substantially the same electric characteristics and an audio amplifying circuit using the combination are also disclosed.

Insulated gate type field effect semiconductor device and a circuit employing the device

PURPOSE:To improve the reliability by forming a 2-layer structure that a base layer is made of a high impurity density layer and a drain region side low impurity density layer, preventing a punch-through phenomenon between the source and the drain and decreasing the base resistance and increasing the breaking strength. CONSTITUTION:An n type epitaxial layer 2 (having 35mum of thickness, 2.0OMEGA.cm of specific resistance) is formed on an n type silicon substrate 1 as a semiconductor substrate. A gate insulating film 3 has 130mum of thickness, a polycrystalline silicon layer having 0.4mum of thickness is formed thereon, and processed as a gate electrode 4. With the electrode 4 as a mask, base layer 5, 6 are formed. This base layer 5 is a p type low impurity density region, and has 6mum of depth, 1X10 cm of surface density. Numeral 6 designates a p type high impurity density region which has 2mum of depth and 3X10 cm of surface density. A source region 7 formed in the base layer 6 is an n type high impurity density layer which has 0.5mum of depth and 2X10 cm of surface density. Numerals 8, 9 designate source and drain electrodes, respectively.

Insulated gate field-effect transistor

Isolierschicht-feldeffekt-halbleiterelemente, schaltungsanordnungen mit derartigen halbleiterelementen und verfahren zur herstellung dieser halbleiterelemente

Masatomo Furumi

Papers

Insulated gate field effect transistor with source field shield extending over multiple region channel

Insulated gate semiconductor device

Insulated gate type field effect semiconductor device and a circuit employing the device

Insulated gate field-effect transistor

Isolierschicht-feldeffekt-halbleiterelemente, schaltungsanordnungen mit derartigen halbleiterelementen und verfahren zur herstellung dieser halbleiterelemente