A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Semiconductor reliability test chip

A field effect transistor used in radio frequency switching applications and having a linear performance characteristic is disclosed. The transistor comprises a plurality of gate lines, a source terminal, a drain terminal, and two feed forward capacitors electrically coupled to the source and drain terminals and the gate line at a plurality of points along the line. An improved transistor preferably includes three or more gate lines to help improve harmonic suppression.

Linearity radio frequency switch with low control voltage

A method is disclosed for packaging an integrated circuit having a heat spreader for cooling an integrated circuit die and glob-topping to both protect bonding wires and attach the heat spreader to a lead frame.

Process for attaching a lead frame to a heat sink using a glob-top encapsulation

PURPOSE:To compose easily a circuit, to prolong the life of a high performance pick-up reproducing needle and a disk and to obtain a recording reproducing device with high reliability by detecting surface vibration of an information recording carrier and controlling the shifting of a reproducing needle by the signal. CONSTITUTION:A disk is reproduced by reading information of a surface of a disk 1 by a detector 3 as a capacity change at the section of a reproducing needle 2 and by sending the information through a signal processing circuit 6 to a display means 7 composed of a speaker, a video tube, etc. An electrode at an upper end of a reproducing needle is electrically connected to a central line of a cavity resonator of the detector 3 by a flylead 8, and when an interval l of a ground of the cavity resonator and the reproducing needle 2 changes in the upward and downward direction by a surface vibration, a return, etc., of the disk 1, a capacity C between the ground and the reproducing needle 2 changes. A cavity resonance frequency is changed by elevating the regenerating needle 2, a signal is amplified by a direct current amplifier, and inputted to a an AFT circuit 13. An output of the AFT circuit 13 is inputted to a coil 18, a pick-up cartridge 15 is operated in the upward and downward direction by an action with a magnet 19 and the electrode of the reproducing needle 2 is controlled so that it may not float.

Recording disk reproducing device

A semiconductor component with a power MOSFET and control circuit for controlling the power MOSFET. Both the power MOSFET and the control circuit have separate semiconductor bodies. The semiconductor body of the control circuit is arranged on one of the main surfaces of the semiconductor body of the power MOSFET. The control circuit is electrically insulated from the MOSFET by an insulating layer and mechanically coupled to the MOSFET by means of a bonding layer. The MOSFET is fastened to a cooling body which serves as a heat sink for the semiconductor component. The terminals of the control circuit and the MOSFET are attached to housing connections with leads.

Semiconductor component with power MOSFET and control circuit

An insulated gate type field effect transistor for high power which has a low conductivity region surrounding a drain region and an offset gate region having a further lower conductivity adjoined thereto, wherein the length and impurity concentration are designed according to the electric characteristics of the transistor. A combination of P channel and N channel type transistors having substantially the same electric characteristics and an audio amplifying circuit using the combination are also disclosed.

Insulated gate type field effect semiconductor device and a circuit employing the device

PURPOSE:To obtain a protective diode for MOSFET without any current leakage, by providing a high impurity-density region beneath a channel inducing insulation film such as a SiO2 film and by cutting the channel, the conductive direction of which has been inverted as the result.

Gate protective diode

Isolierschicht-feldeffekt-halbleiterelemente, schaltungsanordnungen mit derartigen halbleiterelementen und verfahren zur herstellung dieser halbleiterelemente

PURPOSE:To improve an integration degree with the size of either source or drain region reduced, by forming the contact of either source or drain electrode by a self- aligning method. CONSTITUTION:On P-type Si substrate 10, thin gate Si3N4 film 11 and thick poly- crystal Si layer 12 are stacked, and layer 12 is photoetched to obtain gate electrode layers 12A and 12B. Next, N-type impurity ions are implanted into the entire surface to form N -type source region 14 and drain region 15 in substrate 10, and at the same time, electrode layers 12A and 12B are made into low resistances. Through a heat treatment, SiO2 films 16A and 16B are produced on the surfaces of electrode layers 12A and 12B, and they are used as masks to etching and removing film 11, thereby exposing contact regions 17A and 17B to regions 14 and 15. Here, source electrode 18 and drain electrode 19 of Al are adhered respectively. Consequently, contacts to those regions can be formed accurately by the self-aligning method, and an IGFET is miniaturized.

Manufacture of field effect transistor of insulation gate type

PURPOSE:To obtain a high withstand voltage IGFET by lengthening the offset region of an N-channel FET when forming a large power semiconductor device of the N-channel FET having offset gate region and a P-channel FET between a source and a drain. CONSTITUTION:When forming an N-channel FET and a P-channel FET for forming a large power IGFET, the length of the offset gate region of the N- channel FET is formed longer than that of the P-channel FET. In other words, an offset structure P-channel enhancement FET forms a P type drain intermediate region 3 on the surface layer of an N type Si substrate, forms a P type drain region 5 in the region 3, forms a P type source region 2, forms a gate electrode 7 through a gate insulating film therebetween, and forms an offset gate region 4 toward the electrode 7 in the region 3. However, the structure of the N-channel FET is formed similarly, but the length Lreff of the offset gate region 4 is increased at this time.

Takeuchi Masaru

Papers

Insulated gate type field effect semiconductor device and a circuit employing the device

Gate protective diode

Isolierschicht-feldeffekt-halbleiterelemente, schaltungsanordnungen mit derartigen halbleiterelementen und verfahren zur herstellung dieser halbleiterelemente

Manufacture of field effect transistor of insulation gate type

Large power insulated gate field effect semiconductor device