http://cmliris.harvard.edu/assets/science291_851.pdf

Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks

@Aborde trois problematiques dans le contexte de la base de donnees temporelles. Ils sont le probleme de regroupement, la similarite et l'extraction des strategies. Il reste encore des problemes pour les travaux futurs. Par exemple, comment realiser le regroupement graduel pour d'autres algorithmes. Il sera interessant de grouper des sequences en se basant sur notre nouveau modele. Mais les questions posees sont le choix d'un algorithme, ou il faut un nouvel algorithme carrement ? Pour construire une strategie, ce sera aussi possible de pre-definir nos actions. Puis trouver les relations entre les actions et les indicateurs correspondants afin de generer des strategies. . .

Knowledge discovery in time-series databases

Arising from the fourth Dagstuhl conference entitled Visualization and Processing of Tensors and Higher Order Descriptors for Multi-Valued Data (2011), this book offers a broad and vivid view of current work in this emerging field. Topics covered range from applications of the analysis of tensor fields to research on their mathematical and analytical properties.

Visualization and processing of tensors and higher order descriptors for multi-valued data

Low power circuit design has been one of the major growing concerns in integrated circuit technology. Reversible circuit (RC) design is a promising future domain in computing which provides the benefit of less computational power. With the increase in the number of gates and input variables, the circuits become complex and the need for fault testing becomes crucial in ensuring high reliability of their operation. Various fault detection methods based on exhaustive test vector search approaches have been proposed in the literature. With increase in circuit complexity, a faster test generation method for providing optimal coverage becomes desirable. In this paper, a genetic algorithm-based heuristic test set generation method for fault detection in RCs is proposed which avoids the need for an exhaustive search. Two approaches, one involving random search and the other, involving directed search have been proposed and validated on benchmark circuits considering missing-gate fault (complete and partial), bridging fault and stuck-at fault with optimum coverage and reduced computational efforts.

A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits

Quantum-dot cellular automata (QCA) is a paradigm for connecting nanoscale bistable devices to accomplish general-purpose computation. The idea has its origins in the technology of quantum dots, Coulomb blockade, and Landauer’s observations on digital devices and energy dissipation. We examine the early development of this paradigm and its various implementations.

Field-Coupled Nanocomputing

Research in reversible logic is motivated by its application in quantum computing as well as its promise in extremely low power consumption by elimination of power dissipation due to information loss. In this paper we propose a set of novel dual rail reversible logic gates for online testable reversible logic design. Experimental results show that our technique detects 100% of single faults while reducing the area and the number of garbage outputs up to 6.4X and 4.6X, compared to previously proposed techniques, respectively.

Online fault testing of reversible logic using dual rail coding

Reversibility as an inherent requirement of quantum computation motivates further research on reversible logic. Due to anticipated high failure rates for such technologies, thorough testing is a must for these circuits. In this paper, we present a compact test generation and application method for reversible circuits which achieves high (100%) fault coverage and can be adopted for BIST implementations. In this method, the next test pattern is the response of the reversible circuit to the previous test pattern. A test generation algorithm to minimize test time and achieve 100% fault coverage is also presented. Simulation results on a set of reversible benchmark circuits confirm that this approach can detect all single missing/repeated gate faults as well as the majority of multiple faults.

Ping-pong test: Compact test vector generation for reversible circuits

Reversible logic is a promising design methodology, particularly in the scope of quantum computing, for extremely low power consumption by elimination of power dissipation due to information loss. Anticipated high fault rates for future technologies raise demand for fault tolerance in reversible logic. In this paper we propose fault masking techniques (to prevent error propagation) for reversible logic. We present different implementations of reversible majority voters. Using voter insertion techniques and taking advantage of available non-functional outputs, we are able to provide diagnosis information with adjustable resolution for reversible circuits. Such diagnosability has important applications in manufacturing testing as well as online repair. In contrast to previous work this voter is robust against single point of failure. We target missing and repeated gate fault models which are specific to reversible logic.

Fault Masking and Diagnosis in Reversible Circuits

Programmable nano-architectures fabricated based on bottom-up self-assembly process are alternative for CMOS technology to overcome physical barriers as well as increased lithography-based fabrication costs in downscaling Extreme process variation and high failure rate due to nondeter-ministic self assembly fabrication process pose serious challenges for logic implementation in this technology In this paper, we analyze the effect of variations on mapped designs and propose an efficient mapping method to reduce variation effects on crossbar nano-architectures This method takes advantage of reconfigurability and abundance of resources for tolerating variation and improving reliability The main idea is based on duplicating crossbar input lines as well as swapping rows (columns) of a crossbar to reduce the output dependency and be able to reduce delay variation Experimental results on a set of benchmarks show that the proposed method can reduce critical path delay up to 74% (57% in average)

Variation-aware logic mapping for crossbar nano-architectures

Reversible logic is a computation methodology with the promise of possibly zero-energy consumption by elimination of power dissipation due to information loss Furthermore, reversible logic has direct application in quantum computing However, since fault models in reversible circuits are fundamentally different from those used for CMOS VLSI technologies, therefore new testing approaches must be developed to test reversible circuits It has been shown that two new types of faults in the form of gate missing and gate repeating are more likely to occur in reversible circuits, rather than traditional stuck-at faults In this paper, we present an approach for online detection of these types of faults in reversible circuits In this approach, we modify reversible gates in such a way that they can produce information on the number of cascaded gates By using such information we add an appropriate reversible gate to detect missing and repeated gate faults Simulation results on a set of benchmark circuits confirm that the proposed approach can detect 100% of single and more than 97% of multiple missing/repeated gate faults, in average Since, the modified gates provide a combination of basic logic operation (eg NAND and NOR) in a reversible gate, therefore, using these gates effectively reduces area overhead and the number of garbage outputs, compared to previous work

Masoud Zamani

Papers

Online fault testing of reversible logic using dual rail coding

Ping-pong test: Compact test vector generation for reversible circuits

Fault Masking and Diagnosis in Reversible Circuits

Variation-aware logic mapping for crossbar nano-architectures

Online Missing/Repeated Gate Faults Detection in Reversible Circuits