Mehdi B. Tahoori

TL;DR: In this article, the authors introduce the most prominent reliability concerns from today's points of view and roughly recapitulate the progress in the community so far and suggest a way for coping with reliability challenges in upcoming technology nodes.

TL;DR: A detailed simulation-based characterization of QCA defects and study of their effects at logic level are presented and a testing technique requires only a constant number of test vectors to achieve 100% fault coverage with respect to the fault list of the original design.

TL;DR: A new MRAM technology whose writing scheme relies on the Spin Orbit Torque, which offers a very fast switching, a quasi-infinite endurance and improves the reliability by solving the issue of “read disturb”, thanks to separate reading and writing paths.

TL;DR: This paper presents a detailed evaluation of performance and energy related parameters and compares the novel SOT-MRAM with several other memory technologies, and shows that a hybrid-combination of SRAM for the L1-Data-cache, Sot-MRam for theL1-Instruction-cache and L2-cache can reduce the energy consumption and performance while the performance increases by 1% compared to an SRAM-only configuration.

TL;DR: The design and characterization of a novel complex, yet very small, QCA logic gate: the and-or-inverter (AOI) gate is proposed, which performs quite favorably, in terms of digital logic synthesis.