An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

A chemically sensitive sensor with a lightly doped region that affects an overlap capacitance between a gate and an electrode of the chemical sensitive sensor The lightly doped region extends beneath and adjacent to a gate region of the chemical sensitive sensor Modifying the gain of the chemically sensitive sensor is achieved by manipulating the lightly doped region under the electrodes

Chemically sensitive sensor with lightly doped drains

An ion-sensitive circuit can include a charge accumulation device, to accumulate a plurality of charge packets as a function of an ion concentration of a fluid, and at least one control and readout transistor, to generate an output signal as a function of the accumulated plurality of charge packets, the output signal representing the ion concentration of the solution. The charge accumulation device can include a first charge control electrode above a first electrode semiconductor region, an electrically floating gate structure above a gate semiconductor region and below an ion-sensitive passivation surface, a second charge control electrode above a second electrode semiconductor region, and a drain diffusion region. The first control electrode can control entry of charge into a gate semiconductor region in response to a first control signal. The ion-sensitive passivation surface can be configured to receive the fluid. The second charge control electrode can control transmission of the plurality of charge packets out of the gate semiconductor region and into the drain diffusion region in response to a second control signal. The drain diffusion region can receive the plurality of charge packets from the gate semiconductor region via the second electrode semiconductor region.

Ion-sensing charge-accumulation circuits and methods

In one implementation, a chemical sensor is described. The chemical sensor includes chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive sidewall spacer is on a sidewall of the opening and contacts the upper surface of the floating gate conductor.

Chemical sensor with sidewall spacer sensor surface

A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

System for reducing noise in a chemical sensor array

A microcomputer includes a register that stores division ratio setting information, a frequency divider that determines first and second division ratios based on the division ratio setting information, frequency-divides a first clock having a first frequency at the first division ratio, and frequency-divides a second clock having a second frequency at the second division ratio, and a CPU. The first and second division ratios are determined in such a manner that a frequency of the first clock that is frequency-divided at the first division ratio and a frequency of the second clock that is frequency-divided at the second division ratio are made equal to each other.

Clock generation circuit, processor system using same, and clock frequency control method

PROBLEM TO BE SOLVED: To improve communication response in changing the frequency of a system clock signal.SOLUTION: A clock generation circuit CG includes: a system clock selection circuit SEL1 for selecting a system clock signal cks from a first clock signal ck1 and a second clock signal ck2 having mutually different frequencies on the basis of a selection signal ss1; a frequency division circuit 103 for dividing the system clock signal cks to generate plural frequency division clock signals; and a communication clock selection circuit SEL2 for selecting a communication clock signal ckio from the plural frequency division clock signals on the basis of the selection signal ss1 and a division ratio setting signal ss2, and changing a communication clock signal to the selected communication clock signal ckio in synchronization with the timing of switching of the selection signal ss1.

Matsushita Rumi

Papers

Clock generation circuit, processor system using same, and clock frequency control method

Clock generation circuit, processor system using the same and clock frequency control method