Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

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Ultralow-Power Design in Near-Threshold Region

Wireless sensor networks have been gaining interest as a platform that changes how we interact with the physical world. Applications in medicine, military, inventory management, structural and environmental monitoring, and the like can benefit from low-power wireless nodes that communicate data collected via a variety of sensors. Current deployments of wireless sensor networks (WSN) rely on off-the-shelf commodity-based microcontrollers, but the unoptimized energy consumption of these systems can limit the effective lifetimes. Ideally, researchers would like to deeply embed wireless sensor network nodes in the physical world, relying on energy scavenged from the ambient environment. This paper provides a survey of ultra low power processors specifically designed for WSNapplications that have begun to emerge from research labs, which require detailed understanding of tradeoffs between application space, architecture, and circuit techniques to implement these low-power systems.

/pdf/survey-of-hardware-systems-for-wireless-sensor-networks-56i4qjkj8h.pdf

Survey of Hardware Systems for Wireless Sensor Networks

Ultra-Low Power Wake-Up Receivers for Wireless Sensor Networks by Nathan Michael Pletcher Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Jan M. Rabaey, Chair The realization of truly ubiquitous wireless sensor networks (WSN) demands ultra-low power wireless communication capability. Because the radio transceiver consumes power whenever it is active, it most efficient to leave the receiver off and wake it up asynchronously only when needed. A dedicated wake-up receiver can continuously monitor the channel, listening for a wakeup signal from other nodes and activating the main receiver upon detection. By maximizing the node sleep time without compromising network latency, the use of a wake-up receiver can improve overall network performance. Wake-up receivers are also applicable in asymmetric links such as “active” RFID, where the tag listens in standby mode until queried by a reader.

Ultra-low power wake -up receivers for wireless sensor networks

Ultra-low voltage operation is key to achieving energy-efficient operation for microcontroller (MCU) systems. Variation resiliency, high speed operation, and short design time are the most important challenges for these systems. This paper overcomes these challenges in a new design strategy that enables standard cell design with differential transmission gate logic. The commercial toolchain is extended with in-house developed add-ons and makes use of two custom libraries with different device lengths to allow high speed vs. low leakage trade-offs. The design flow is used to prototype two highly efficient 32-bit ARM Cortex-M0 MCU systems in 40-nm CMOS. The core of the first prototype scales down to 190 mV and 0.8-MHz and reaches 16.07 pJ/cycle at 31.2-MHz and 440 mV. The second prototype benefits from the dual libraries and reduces core energy consumption by 50% at the same speed performance. Minimum energy operation is thus achieved at an even lower voltage (370 mV) with the M0 core consuming only 8.80 pJ/cycle at 13.7-MHz, breaking the sub-10-pJ/cycle barrier for a 6–35-MHz range.

/pdf/a-differential-transmission-gate-design-flow-for-minimum-26z8krcy3o.pdf

A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs

This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.

Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic

This paper shows leakage as a limit to the effectiveness of voltage scaling as a means of reducing the energy per operation in a digital circuit. Methods of decreasing operational or dynamic leakage are then discussed. The design and simulation results of a sense amplifier-based pass transistor logic (SAPTL) circuit topology as a low leakage and low energy alternative is presented and then compared to standard static 90-nm CMOS implementations.

Matthew D. Pierson

Papers

Exploring Very Low-Energy Logic: A Case Study