IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

A method is provided for modifying an image. The method comprises displaying an image, the image comprising a portion of an object; and determining if an edge of the object is in a location within the portion. The method further comprises detecting movement, in a member direction, of an operating member with respect to the edge. The method still further comprises moving, if the edge is not in the location, the object in an object direction corresponding to the detected movement; and modifying, if the edge is in the location, the image in response to the detected movement, the modified image comprising the edge in the location.

Information processing apparatus, information processing method and program

This paper presents a modular and extensible high-level synthesis research system, called SPARK, that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL. SPARK uses parallelizing compiler technology, developed previously, to enhance instruction-level parallelism and re-instruments it for high-level synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware cost models. In this paper, we present the design flow through the SPARK system, a set of transformations that include speculative code motions and dynamic transformations and show how these transformations and other optimizing synthesis and compiler techniques are employed by a scheduling heuristic. Experiments are performed on two moderately complex industrial applications, namely MPEG-1 and the GIMP image processing tool. The results show that the various code transformations lead to up to 70 % improvements in performance without any increase in the overall area and critical path of the final synthesized design.

/pdf/spark-a-high-level-synthesis-framework-for-applying-5we3vt5f39.pdf

SPARK: a high-level synthesis framework for applying parallelizing compiler transformations

http://www.cas.mcmaster.ca/~sancheg/EE_UCU2006_thesis/biblio/Methods%20for%20Evaluating%20and%20Covering%20the%20Design%20Space%20during%20Early%20Design%20Development%20%28ucb-erl_m03-32_DSE_survey%29.pdf

Methods for evaluating and covering the design space during early design development

Methods, devices and systems for detecting suspicious or performance-degrading mobile device behaviors intelligently, dynamically, and/or adaptively determine computing device behaviors that are to be observed, the number of behaviors that are to be observed, and the level of detail or granularity at which the mobile device behaviors are to be observed. The various aspects efficiently identify suspicious or performance-degrading mobile device behaviors without requiring an excessive amount of processing, memory, or energy resources.

Adaptive Observation of Behavioral Features on a Mobile Device

Methods, systems and devices for generating data models in a client-cloud communication system may include applying machine learning techniques to generate a first family of classifier models that describe a cloud corpus of behavior vectors. Such vectors may be analyzed to identify factors in the first family of classifier models that have the highest probability of enabling a mobile device to better determine whether a mobile device behavior is malicious or benign. Based on this analysis, a second family of classifier models may be generated that identify significantly fewer factors and data points as being relevant for enabling the mobile device to better determine whether the mobile device behavior is malicious or benign based on the determined factors. A mobile device classifier module based on the second family of classifier models may be generated and made available for download by mobile devices, including devices contributing behavior vectors.

On-line behavioral analysis engine in mobile device with multiple analyzer model providers

Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure, performance is the most important feature of an instruction-set simulator. Interpretive simulators are flexible but slow, whereas compiled simulators deliver speed at the cost of flexibility. This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation. We achieve fast instruction accurate simulation through two mechanisms. First, we move the time-consuming decoding process from run-time to compile time while maintaining the flexibility of the interpretive simulation. Second, we use a novel instruction abstraction technique to generate aggressively optimized decoded instructions that further improves simulation performance. Our instruction set compiled simulation (IS-CS) technique delivers up to 40% performance improvement over the best known published result that has the flexibility of the interpretive simulation. We illustrate the applicability of the IS-CS technique using the ARM7 embedded processor.

/pdf/instruction-set-compiled-simulation-a-technique-for-fast-and-53alsyr7mr.pdf

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation

The aspects include browser systems and methods of loading/rendering a webpage by processing the web document (HTML page) in parallel. A scanner process scans the web document, identifies scripts, and initiates the downloading of the scripts. As the scripts are downloaded, an HTML parser generates an identifier for each script and the sends the scripts and associated identifiers to a script engine. The script engine parses, analyzes, compiles, and otherwise prepares the scripts for execution in an order that may be different than the execution order of the scripts.

Pre-processing of scripts in web browsers

Methods and devices include a server and at least two web browsers operable on at least two different computing devices. Each browser reports results of processing and rendering of webpages to the server. The server aggregates the data. The server generates metadata from the aggregated browsers. The server transmits the generated metadata to at least one computing device. The computing device renders a webpage using at least a portion of the provided metadata. The metadata may identify portions of JavaScript that can be processed in parallel. The metadata may identify a library portion that does not have to be loaded. The metadata may identify a portion of the webpage that may be rendered first before a second portion of the webpage. Returning metadata to the computing device can assist the computing device in parsing, analyzing or executing the request for the webpage.

Web browsing enhanced by cloud computing

Instruction-set architecture (ISA) simulators are an integral part of today's processor and software design process. While increasing complexity of the architectures demands high performance simulation, the increasing variety of available architectures makes retargetability a critical feature of an instruction-set simulator. Retargetability requires generic models while high performance demands target specific customizations. To address these contradictory requirements, we have developed a generic instruction model and a generic decode algorithm that facilitates easy and efficient retargetability of the ISA-simulator for a wide range of processor architectures such as RISC, CISC, VLIW and variable length instruction set processors. The instruction model is used to generate compact and easy to debug instruction descriptions that are very similar to that of architecture manual. These descriptions are used to generate high performance simulators. The generation of the simulator is completely separate from the simulation engine. Hence, we can incorporate any fast simulation technique in our retargetable framework without loosing performance. We illustrate the retargetability of our approach using two popular, yet different realistic architectures: the Sparc and the ARM.

/pdf/an-efficient-retargetable-framework-for-instruction-set-82ov3i71l4.pdf

Mehrdad Reshadi

Papers

On-line behavioral analysis engine in mobile device with multiple analyzer model providers

Instruction set compiled simulation: a technique for fast and flexible instruction set simulation

Pre-processing of scripts in web browsers

Web browsing enhanced by cloud computing

An efficient retargetable framework for instruction-set simulation