Integration of multiple heterogeneous processors into a single system-on-a-chip is a clear trend in embedded devices. Designing and verifying these devices requires high-speed and easy-to-build simulation platforms. Among the software simulation approaches, native simulation is a good candidate since the embedded software is executed natively on the host machine, and no instruction set simulator development effort is necessary. However, existing native simulation approaches are such that the simulated software shares the memory space of the modeled hardware modules and the host operating system, making impractical the support of legacy code running on the target platform. To overcome this issue seldom mentioned in the literature, we propose the addition of a transparent address space translation layer to separate the target address space from the host simulator one. For this, we exploit the hardware-assisted virtualization technology now available on most general-purpose processors. Experiments show that this solution does not degrade the native simulation speed, while keeping the ability to accomplish software performance evaluation.

Native Simulation of MPSoC Using Hardware-Assisted Virtualization

Migrating a process from a source system with a source operating system to a target system with a target operating system is provided, where the source and target systems or source and target operating system are incompatible. The migrating includes: employing an emulator at the target system to execute code associated with the process being migrated, the emulator performing: translating of system calls and runtime library calls for the source operating system to calls of the target operating system using a system call translator and runtime library translator; translating source application code associated with the process into binary target application code executable on the target system, using a compiler where the source application code has not been translated; and executing the translated binary target application code on the target system, and discontinuing emulation of the process at the target system once the executing begins.

Method and system for migration of processes in heterogeneous computing environments

We introduce a static binary translation flow in native simulation context for cross-compiled VLIW executables. This approach is interesting in situations where either the source code is not available or the target platform is not supported by any retargetable compilation framework, which is usually the case for VLIW processors. The generated simulators execute on a Hardware-Assisted Virtualization (HAV) based native platform. We have implemented this approach for a TI C6x series processor and our simulation results show a speed-up of around two orders of magnitude compared to the cycle accurate simulators.

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Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization

Virtual prototyping of MPSoCs requires fast processor simulation models. Dynamic binary translation is an efficient technology for instruction set simulation, but as it is basically used for effortless code migration, it targets mostly general purpose processors. As many heterogeneous MPSoCs include VLIW processors, we propose and detail in this paper a strategy to perform dynamic binary translation of VLIW codes on scalar architectures for simulation purposes. Our simulation experiments show that it is a few orders of magnitude faster than direct instruction interpretation, although the translator includes no optimization.

Fast simulation of systems embedding VLIW processors

Implementing on-chip multiprocessors is enabled by the use of deep submicron technologies and constitutes today a daunting task, due to the complexity of their design and verification. The development of such devices can be facilitated by the use of a carefully crafted set of models for each implementation step. This paper proposes the use of such a set of abstract models at several levels. These improve simulation speed and observability in one sense and level of detail and precision in the opposite sense. Initial development tasks such as software development and functionality specification refinement can evolve fast with very abstract models, while confidence in the final implementation can be achieved with lower level models. Our basic multi-processor system on a chip is configurable in several parameters, including number of processors, type of employed communication architecture and combination of abstraction levels used in the description of the distinct modules that compose the model.

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A spectrum of MPSoC models for design space exploration and its use

This article presents a wide variety of techniques for realizing transaction-level models of the increasingly large-scale multiprocessor systems on chip. It describes how such models of hardware allow subsequent software integration and system performance evaluation.

Mian-Muhammed Hamayun

Papers

On MPSoC Software Execution at the Transaction Level