An output driver circuit is described which offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtain different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry are described for improving high frequency operation.

Adjustable output driver circuit

An output driver circuit offers control and logic level adjustment for high speed data communications in a synchronous memory such as a synchronous dynamic random access memory (SDRAM). Level adjustment is obtained by resistive division between a termination resistor and controllable impedances between an output node and VDD and VSS power supplies. Control functions include slew rate modification of the signal at the output node, by sequentially turning on or off output transistors in response to a transition in an input signal. Different schemes of weighting the output transistors obtains different characteristics of the output signal. Load matching circuitry and voltage level forcing circuitry is described for improving high frequency operation.

Adjustable output driver circuit having parallel pull-up and pull-down elements

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

The present invention relates to a semiconductor memory device. A charge recycling circuit is driven to raise a potential of a restore node and a sensing bar node to a given potential before a sensing operation is performed, and electric charges discharged from the restore node and the sensing bar node are stored using the charge recycling circuit and are then used when a next sensing operation is performed, after the sensing operation is performed, depending on a control signal outputted from a control signal generating circuit. Therefore, current consumed when the sensing operation is performed can be reduced and the power consumption can be thus significantly reduced.

Semiconductor memory device

A semiconductor memory device is provided to perform high speed operation by removing unnecessary operation margin. A semiconductor memory device comprises a memory cell transistor(MT), a bit line connected to the memory cell transistor and a sense amplifier(12). The sense amplifier is enabled by a sense enable signal and senses a voltage of the bit line. A first dummy bit line is connected to a first dummy memory cell transistor, and has a line load larger than the bit line. A first detection circuit(17) detects a voltage of the first dummy bit line. A precharge circuit charges a voltage of the first dummy bit line. A second dummy bit line is connected to a second dummy memory cell transistor, and has a line load larger than the bit line. A discharging circuit discharges the bit line and the second dummy bit line. A second detection circuit(19) detects a voltage of the second dummy bit line. A read control circuit(13) starts charging operation of the precharge circuit according to a read enable signal, and stops the charging operation of the precharge circuit according to a first detection signal of the first detection circuit, and starts discharging operation of the discharging circuit, and outputs the sense enable signal according to a second detection signal of the second detection circuit.

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Low leakage and data retention circuitry

A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.

Digital output buffer and method with slew rate control and reduced crowbar current

Reduced switching noise output buffer using diode for quick turn-off

Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Method and apparatus for design of integrated circuits

Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Michael A. Zampaglione

Papers

Low leakage and data retention circuitry

Digital output buffer and method with slew rate control and reduced crowbar current

Reduced switching noise output buffer using diode for quick turn-off

Method and apparatus for design of integrated circuits

Method and apparatus for integrated circuit design with library cells