This paper presents a low-complexity algorithm and architecture to compute power spectral density (PSD) using the Welch method. The Welch algorithm provides a good estimate of the spectral power at the cost of high computational complexity. We propose a new modified approach to reduce the computational complexity of the Welch PSD computation for a 50% overlap. In the proposed approach, an N/2-point FFT is computed, where N is the length of the window and is merged with the FFT of the previous N/2-point to generate an N-point FFT of the overlapped segment. This requires replacing the windowing operation as a convolution in the frequency domain. Fortunately, the frequency-domain filtering requires a symmetric 3-tap or 5-tap FIR filter for raised cosine windows. The proposed method needs to compute ( L+1) N/2-point FFTs instead of L N-point FFTs, where L is the number of overlapping segments. In the proposed novel merged FFT approach, the even samples are computed exactly, while the odd samples require a shift by a half-sample delay and are estimated using a bidirectional fractional-delay filter. The complexity reduction comes at the cost of slight performance loss due to the approximation used for the implementation of the fractional-delay filter. The performance loss is about 8% using fractional-delay filter with 2 multipliers. A novel architecture is presented based on the proposed algorithm. The proposed architecture not only consumes 33% less energy compared to the original method but also reduces the latency by about 44% for 8 overlapping segments. Further a low-complexity architecture is presented to compute a special case of the short-time Fourier transform based on the proposed PSD computation algorithm.

Low-Complexity Welch Power Spectral Density Computation

This paper presents compact yet comprehensive feature representations for the electroencephalogram (EEG) signal to achieve efficient epileptic seizure prediction performance. The initial EEG feature vectors are formed by acquiring the dominant amplitude and frequency components on an epoch-by-epoch basis from the EEG signals. These extracted parameters can reveal the intrinsic EEG signal changes as well as the underlying stage transitions. To improve the efficacy of feature extraction, an elimination-based feature selection method has been applied on the initial feature vectors. This diminishes redundant and noisy points, providing each patient with a lower dimensional and independent final feature form. In this context, our study is distinguished from that of others currently prevailing. Usually, these latter approaches adopted feature extraction processes, which employed time-consuming high-dimensional parameter sets. Machine learning approaches that are considered as state of the art have been employed to build patient-specific binary classifiers that can divide the extracted feature parameters into preictal and interictal groups. Through out-of-sample evaluation on the intracranial EEG recordings provided by the publicly available Freiburg dataset, promising prediction performance has been attained. Specifically, we have achieved 98.8% sensitivity results on the 19 patients included in our experiment, where only one of 83 seizures across all patients was not predicted. To make this investigation more comprehensive, we have conducted extensive comparative studies with other recently published competing approaches, in which the advantages of our method are highlighted.

Extracting and Selecting Distinctive EEG Features for Efficient Epileptic Seizure Prediction

We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes $\log _{2}\textit {N}-1$ SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to $\log _{4}\textit {N}-0.5$ , compared with $\log _{2}\textit {N}-1$ for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders $\log _{2}\textit {N}+1$ and complex delay memory $2\textit {N}+1.5\log _{2}\textit {N}-1.5$ .

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.

An In-Place FFT Architecture for Real-Valued Signals

This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths The imaginary parts of the computations replace the redundant operations in the modified flow graph New butterfly structures are designed to handle the hybrid datapaths The proposed hybrid datapath leads to a general approach which can be extended to all radix- 2n based FFT algorithms Further, architectures with arbitrary level of parallelism can be derived using the folding methodology Novel 2-parallel and 4-parallel architectures are presented for radix- 23 and radix- 24 algorithms The proposed architectures maximize the utilization of hardware components with no redundant computations The proposed radix- 23 and radix- 24 architectures lead to low hardware complexity with respect to adders and delays The N-point 4-parallel radix- 24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements

FFT Architectures for Real-Valued Signals Based on Radix- $2^{3}$ and Radix- $2^{4}$ Algorithms

This paper presents a novel approach to develop parallel pipelined architectures for the fast Fourier transform (FFT). A formal procedure for designing FFT architectures using folding transformation and register minimization techniques is proposed. Novel parallel-pipelined architectures for the computation of complex and real valued fast Fourier transform are derived. For complex valued Fourier transform (CFFT), the proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. Further, this paper presents new parallel-pipelined architectures for the computation of real-valued fast Fourier transform (RFFT). The proposed architectures exploit redundancy in the computation of FFT samples to reduce the hardware complexity. A comparison is drawn between the proposed designs and the previous architectures. The power consumption can be reduced up to 37% and 50% in 2-parallel CFFT and RFFT architectures, respectively. The output samples are obtained in a scrambled order in the proposed architectures. Circuits to reorder these scrambled output sequences to a desired order are presented.

Pipelined Parallel FFT Architectures via Folding Transformation

The present invention relates to the design and implementation of parallel pipelined circuits for the fast Fourier transform (FFT). In this invention, an efficient way of designing FFT circuits using folding transformation and register minimization techniques is proposed. Based on the proposed scheme, novel parallel-pipelined architectures for the computation of complex fast Fourier transform are derived. The proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The proposed circuits process L consecutive samples from a single-channel signal in parallel. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. The proposed scheme is general and suitable for applications such as communications, biomedical monitoring systems, and high speed OFDM systems.

Parallel pipelined systems for computing the fast fourier transform

A new low complexity seizure prediction algorithm is proposed. The algorithm achieves high sensitivity and low false positive rates in 10 out of 18 epileptic patients from the Freiburg database. Its primary achievement is two orders of magnitude computational complexity reduction. The reduced complexity makes an implantable medical device application realizable. In the subset of ten highly predictable patients average sensitivity is 96%, average specificity is 0.25 false positives per hour, and 13.5% of time is spent in false alarms. For all eighteen patients tested, the average sensitivity is 83%, the average specificity is 0.38 false positives per hour, and the amount of time spent in false alarms is 21.1%. This result may be compared with sensitivity of 97.5%, specificity of 0.27 false positives per hour, and 13% of time is spent in false alarms of prior results without complexity reduction.

Michael J. Brown

Papers

Pipelined Parallel FFT Architectures via Folding Transformation

Parallel pipelined systems for computing the fast fourier transform

A low complexity seizure prediction algorithm