algorithmics and modular computations, Theory of Codes and Cryptography (3).From an analytical 1. RE Blahut. Theory and practice of error control codes. eecs.uottawa.ca/∼yongacog/courses/coding/ (3) R.E. Blahut,Theory and Practice of Error Control Codes, Addison Wesley, 1983. QA 268. Cached. Download as a PDF 457, Theory and Practice of Error Control CodesBlahut 1984 (Show Context). Citation Context..ontinued fractions.

Theory and practice of error control codes

Large-scale deep neural networks (DNNs) are both compute and memory intensive. As the size of DNNs continues to grow, it is critical to improve the energy efficiency and performance while maintaining accuracy. For DNNs, the model size is an important factor affecting performance, scalability and energy efficiency. Weight pruning achieves good compression ratios but suffers from three drawbacks: 1) the irregular network structure after pruning, which affects performance and throughput; 2) the increased training complexity; and 3) the lack of rigirous guarantee of compression ratio and inference accuracy.To overcome these limitations, this paper proposes CirCNN, a principled approach to represent weights and process neural networks using block-circulant matrices. CirCNN utilizes the Fast Fourier Transform (FFT)-based fast multiplication, simultaneously reducing the computational complexity (both in inference and training) from $\mathrm {O}(n^{2})$ to $\mathrm {O}(n$ log n) and the storage complexity from $\mathrm {O}(n^{2})$ to O(n), with negligible accuracy loss. Compared to other approaches, CirCNN is distinct due to its mathematical rigor: the DNNs based on CirCNN can converge to the same “effectiveness” as DNNs without compression. We propose the CirCNN architecture, a universal DNN inference engine that can be implemented in various hardware/software platforms with configurable network architecture (e.g., layer type, size, scales, etc In CirCNN architecture: 1) Due to the recursive property, FFT can be used as the key computing kernel which ensures universal and small-footprint implementations. 2) The compressed but regular network structure avoids the pitfalls of the network pruning and facilitates high performance and throughput with highly pipelined and parallel design. To demonstrate the performance and energy efficiency, we test CIR-CNN in FPGA, ASIC and embedded processors. Our results show that CirCNN architecture achieves very high energy efficiency and performance with a small hardware footprint. Based on the FPGA implementation and ASIC synthesis results, CirCNN achieves 6 - 102X energy efficiency improvements compared with the best state-of-the-art results.CCS Concepts• Computer systems organization$\rightarrow $ Embedded hardware;

CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices

Epileptic seizure prediction using relative spectral power features.

Prediction of seizures is a difficult problem as the EEG patterns are not wide-sense stationary and change from seizure to seizure, electrode to electrode, and from patient to patient. This paper presents a novel patient-specific algorithm for prediction of seizures in epileptic patients from either one or two single-channel or bipolar channel intra-cranial or scalp electroencephalogram (EEG) recordings with low hardware complexity. Spectral power features are extracted and their ratios are computed. For each channel, a total of 44 features including 8 absolute spectral powers, 8 relative spectral powers and 28 spectral power ratios are extracted every two seconds using a 4-second window with a 50% overlap. These features are then ranked and selected in a patient-specific manner using a two-step feature selection. Selected features are further processed by a second-order Kalman filter and then input to a linear support vector machine (SVM) classifier. The algorithm is tested on the intra-cranial EEG (iEEG) from the Freiburg database and scalp EEG (sEEG) from the MIT Physionet database. The Freiburg database contains 80 seizures among 18 patients in 427 hours of recordings. The MIT EEG database contains 78 seizures from 17 children in 647 hours of recordings. It is shown that the proposed algorithm can achieve a sensitivity of 100% and an average false positive rate (FPR) of 0.0324 per hour for the iEEG (Freiburg) database and a sensitivity of 98.68% and an average FPR of 0.0465 per hour for the sEEG (MIT) database. These results are obtained with leave-one-out cross-validation where the seizure being tested is always left out from the training set. The proposed algorithm also has a low complexity as the spectral powers can be computed using FFT. The area and power consumption of the proposed linear SVM are 2 to 3 orders of magnitude less than a radial basis function kernel SVM (RBF-SVM) classifier. Furthermore, the total energy consumption of a system using linear SVM is reduced by 8% to 23% compared to system using RBF-SVM.

Low-Complexity Seizure Prediction From iEEG/sEEG Using Spectral Power and Ratios of Spectral Power

This paper presents a novel approach to develop parallel pipelined architectures for the fast Fourier transform (FFT). A formal procedure for designing FFT architectures using folding transformation and register minimization techniques is proposed. Novel parallel-pipelined architectures for the computation of complex and real valued fast Fourier transform are derived. For complex valued Fourier transform (CFFT), the proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. Further, this paper presents new parallel-pipelined architectures for the computation of real-valued fast Fourier transform (RFFT). The proposed architectures exploit redundancy in the computation of FFT samples to reduce the hardware complexity. A comparison is drawn between the proposed designs and the previous architectures. The power consumption can be reduced up to 37% and 50% in 2-parallel CFFT and RFFT architectures, respectively. The output samples are obtained in a scrambled order in the proposed architectures. Circuits to reorder these scrambled output sequences to a desired order are presented.

Pipelined Parallel FFT Architectures via Folding Transformation

This paper presents a low-complexity algorithm and architecture to compute power spectral density (PSD) using the Welch method. The Welch algorithm provides a good estimate of the spectral power at the cost of high computational complexity. We propose a new modified approach to reduce the computational complexity of the Welch PSD computation for a 50% overlap. In the proposed approach, an N/2-point FFT is computed, where N is the length of the window and is merged with the FFT of the previous N/2-point to generate an N-point FFT of the overlapped segment. This requires replacing the windowing operation as a convolution in the frequency domain. Fortunately, the frequency-domain filtering requires a symmetric 3-tap or 5-tap FIR filter for raised cosine windows. The proposed method needs to compute ( L+1) N/2-point FFTs instead of L N-point FFTs, where L is the number of overlapping segments. In the proposed novel merged FFT approach, the even samples are computed exactly, while the odd samples require a shift by a half-sample delay and are estimated using a bidirectional fractional-delay filter. The complexity reduction comes at the cost of slight performance loss due to the approximation used for the implementation of the fractional-delay filter. The performance loss is about 8% using fractional-delay filter with 2 multipliers. A novel architecture is presented based on the proposed algorithm. The proposed architecture not only consumes 33% less energy compared to the original method but also reduces the latency by about 44% for 8 overlapping segments. Further a low-complexity architecture is presented to compute a special case of the short-time Fourier transform based on the proposed PSD computation algorithm.

Low-Complexity Welch Power Spectral Density Computation

Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. The contribution of this paper is two fold. First, this paper presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all generator polynomials used in CRC operations and BCH encoders. Second, a new formulation is proposed to modify the LFSR into the form of an infinite impulse response (IIR) filter. We propose a novel high speed parallel LFSR architecture based on parallel IIR filter design, pipelining and retiming algorithms. The advantage of the proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. The proposed parallel architecture achieves better area-time product compared to the previous designs.

High-Speed Parallel Architectures for Linear Feedback Shift Registers

This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.

An In-Place FFT Architecture for Real-Valued Signals

This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths The imaginary parts of the computations replace the redundant operations in the modified flow graph New butterfly structures are designed to handle the hybrid datapaths The proposed hybrid datapath leads to a general approach which can be extended to all radix- 2n based FFT algorithms Further, architectures with arbitrary level of parallelism can be derived using the folding methodology Novel 2-parallel and 4-parallel architectures are presented for radix- 23 and radix- 24 algorithms The proposed architectures maximize the utilization of hardware components with no redundant computations The proposed radix- 23 and radix- 24 architectures lead to low hardware complexity with respect to adders and delays The N-point 4-parallel radix- 24 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements

Manohar Ayinala

Papers

Pipelined Parallel FFT Architectures via Folding Transformation

Low-Complexity Welch Power Spectral Density Computation

High-Speed Parallel Architectures for Linear Feedback Shift Registers

An In-Place FFT Architecture for Real-Valued Signals

FFT Architectures for Real-Valued Signals Based on Radix- $2^{3}$ and Radix- $2^{4}$ Algorithms