Achieving high linearity and bandwidth with good power efficiency makes the design of ADCs in deep nanoscale CMOS processes very challenging, as the constraints of low-voltage operation and limited intrinsic gain often dictate the use of power-consuming analog circuits and intensive digital calibration. This paper addresses these problems by introducing a pipelined ADC that exploits the low but very constant open-loop gain versus output voltage characteristic of the ring amplifier (ringamp) to achieve both high speed and linearity in low-voltage nanoscale CMOS designs. A tunable ringamp biasing scheme using an anti-parallel arrangement of CMOS transistors and an active ringamp-based common-mode feedback are also introduced. A single-channel prototype ADC is implemented in a standard 28-nm CMOS process, achieving 58.7-dB SNDR and 72.4-dB SFDR at 600 MS/s while consuming 14.5 mW from a single 0.9-V supply, resulting in Walden and Schreier figure-of-merit (FoM) values of 34.4 fJ/conv.-step and 161.9 dB, respectively.

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS

In this paper, process invariant biasing is proposed for robust operation of ring amplifiers. The ring amplifier is an efficient solution for high accuracy amplification in sub-micron CMOS process. A traditional ring amplifier structure requires an external control voltage, defined as the deadzone voltage, to set the optimum quiescent current at the output stage. Other structures of ring amplifiers use on-chip resistors or current starved inverters to set the deadzone voltage. Since the deadzone voltage is a function of the threshold voltage of transistors in the output stage inverter, ring amplifiers are susceptible to process variations. In this paper, a deadzone regulation circuit is proposed that utilizes a constant current source and a negative feedback loop to regulate the quiescent current of the output stage inverter across process corners. Transistor level simulations are used to validate the operation of the proposed deadzone regulation technique across FF, TT and SS corners in a 65nm CMOS process. The design example uses a current starved inverter based ring amplifier in a switched capacitor amplifier to achieve a closed loop gain of 4 with a settling accuracy of ≤ 0.05% and operated at a sampling rate of 125MHz.

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit

This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A “split-reference” regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing overall buffer design requirements and improving efficiency. The regulator blocks are implemented with fully dynamic discrete-time loops. Furthermore, a technique for background reconstruction of residue amplifier settling behavior is also described. The “scope-on-chip” captures high-resolution transient waveforms using a 1-bit stochastic ADC. It is shown how these waveform data can be used for optimization of ringamp biasing and PVT tracking. The ADC is fabricated in a 16-nm CMOS technology and at 1 GS/s with a Nyquist input achieves 59.5-dB SNDR, 75.9-dB SFDR, and 10.9-mW total power consumption with only 8% consumed by the reference regulation.

A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm

Reliability and cost efficiency are of utmost importance for cryptographic key generation and storage in IoT applications. This paper presents a 2T2R RRAM PUF scheme with assisting circuit techniques for dense and reliable cryptographic key generation in 28nm logic process. The set time mismatch in two adjacent RRAM devices is exploited for PUF output with better tolerance against PVTA variations. Array architecture featuring interleaved cell mirroring improves the randomness by eliminating the systematic deviation. Self-adaptive splitting with current limiter eliminates the negative effect of mismatch in the peripheral circuits and suppresses the undue duration of large operation current. Silicon data demonstrates our RRAM PUF passes NIST test with intrachip Hamming distance (HD) of 0, inter-chip HD of 0.496 and bit error rate of <1×10−5@0-120 °C. The cell size of 2T2R PUF is 0.54 µm2 and can be reduced when the selector is shared or the RRAM set/reset voltages are optimized below the core supply voltage.

A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key

This work presents a design example of how ring amplifier settling differs from a traditional operational amplifier. Ringamps posses dynamic bandwidth characteristics when amplifying discrete-time waveforms. The dynamic bandwidth of ringamps is demonstrated with transistor level simulations in an 180 CMOS process. That experiment shows increased performance when used in low feedback factors compared to operational amplifiers. This work includes a discussion on how the settling performance of ringamps affects system level analog-to-digital converter design.

An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs

In this paper, passive compensation techniques are proposed: to improve the settling performance of a ring amplifier and to minimize the power consumption of ring amplifiers in high speed applications. The ring amplifier is an efficient solution for high accuracy amplification in sub-micron CMOS process. However, due to the multi stage structure of the ring amplifier, the need for stabilization increases the static power consumption of the amplifier in high speed and high accuracy applications. The proposed technique utilizes LHP zeros obtained from the switches in a switched capacitor feedback network to stabilize the large signal and small signal response of a ring amplifier. Transistor level simulations are used to validate the effect of passive compensation in a 65nm CMOS process. The ring amplifier is designed for an output settling accuracy of ≤0.02% and operated at 150MHz sampling rate. Using the proposed technique, transistor level simulation shows a 72% reduction in static power in comparison to the traditional compensation methods.

Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers

The design of a successive approximation analog-to-digital converter with dynamic redundancy algorithm is proposed. The dynamic redundancy algorithm reduces comparator pre-amplifier activity by completing conversions at an accelerated speed and powering-down early. When bit decisions are restricted to incomplete settling in the DAC and comparator pre-amplifier, errors in the SAR algorithm will occur. The dynamic redundancy algorithm examines the digital word for these errors. Once the algorithm detects errors, the SAR ADC continues the successive approixmation algorithm through an auxiliary DAC. The architecture is shown through simulation to reduce comparator pre-amplifier activity down to 28% in comparison to architectures with uniform timing algorithms.

Michael Oatman

Papers

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit

An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs

Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers

A Power Efficient SAR Algorithm for High Resolution ADCs