A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Semiconductor device and method for fabricating the same

A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material along the sidewalls of the features in the first material.

Self-trimming method on looped patterns

A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Method for forming pitch independent contacts and a semiconductor device having the same

A silicon oxide film is formed on a silicon substrate with a diffusion layer, and a contact hole is formed in the silicon oxide film. A protective film made of an oxide film and a nitride film is formed over the whole surface of the substrate, and the contact hole is buried with a BPSG film. Another silicon oxide film is deposited over the substrate and an interconnection trench is formed in this silicon oxide film. After the BPSG film is removed, a TiN/Ti film is formed over the whole surface of the substrate. A Cu film is grown by MO-CVD, and thereafter the Cu film and TiN/Ti film on the surface of the substrate are partially removed by CMP. A highly reliable contact plug and a trench burying higher level interconnection are formed even where contacts are margin-less or where alignment errors are present.

Method for fabricating semiconductor device with interconnections buried in trenches

A semiconductor device and process for making the same are disclosed which incorporate organic dielectric materials to form self-aligned contacts (SACTs) reliably, even in deep, narrow gaps. In one embodiment, conductors 26 with insulating conductor caps 28 are formed over a silicon substrate 20 with a thin gate oxide 22. A conformal dielectric layer 30, preferably of thermally-grown oxide, is deposited over this structure, which is then covered with an organic-containing layer 32 and an inorganic cap layer 34 (e.g., CVD TEOS). An etch window 38 is patterned in photoresist layer 36 and used as a mask to etch cap window 39 through layer 34, using layer 32 as an etch stop. A second etch removes organic-containing layer 32 in contact window 41 (and preferably strips photoresist), using conformal layer 30 as an etch stop. A short anisotropic etch may be used to clear conformal layer 30 from gap bottom 43, after which conducting material 40 may be used to make electrical contact to the substrate.

Method of fabricating a self-aligned contact using organic dielectric materials

The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer. Since the second insulating material remains in only selective areas, the process is termed selective planarization. The method provides the benefit that areas which are to be etched to form contact hole or vias are not planarized, unlike existing blanket planarization methods, and a self-aligned contact is formed between the conductive members to the substrate.

Michael P. Woo

Papers

Method for forming a multi-layer semiconductor device using selective planarization