A method of generating a signal comprising providing a capacitive touch sensor pad including a matrix of X and Y conductors, developing capacitance profiles in one of an X direction and a Y direction from the matrix of X and Y conductors, determining an occurrence of a single gesture through an examination of the capacitance profiles, the single gesture including an application of at least two objects on the capacitive touch sensor pad, and generating a signal indicating the occurrence of the single gesture.

Object position detector with edge motion feature and gesture recognition

Disclosed herein are liquid-crystal display (LCD) touch screens that integrate the touch sensing elements with the display circuitry. The integration may take a variety of forms. Touch sensing elements can be completely implemented within the LCD stackup but outside the not between the color filter plate and the array plate. Alternatively, some touch sensing elements can be between the color filter and array plates with other touch sensing elements not between the plates. In another alternative, all touch sensing elements can be between the color filter and array plates. The latter alternative can include both conventional and in-plane-switching (IPS) LCDs. In some forms, one or more display structures can also have a touch sensing function. Techniques for manufacturing and operating such displays, as well as various devices embodying such displays are also disclosed.

Touch screen liquid crystal display

An electronic–photonic microprocessor chip manufactured using a conventional microelectronics foundry process is demonstrated; the chip contains 70 million transistors and 850 photonic components and directly uses light to communicate to other chips. The rapid transfer of data between chips in computer systems and data centres has become one of the bottlenecks in modern information processing. One way of increasing speeds is to use optical connections rather than electrical wires and the past decade has seen significant efforts to develop silicon-based nanophotonic approaches to integrate such links within silicon chips, but incompatibility between the manufacturing processes used in electronics and photonics has proved a hindrance. Now Chen Sun et al. describe a 'system on a chip' microprocessor that successfully integrates electronics and photonics yet is produced using standard microelectronic chip fabrication techniques. The resulting microprocessor combines 70 million transistors and 850 photonic components and can communicate optically with the outside world. This result promises a way forward for new fast, low-power computing systems architectures. Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome1,2,3 by using optical communications based on chip-scale electronic–photonic systems4,5,6,7 enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic–photonic chips9,10,11 are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic–photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics12, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors13,14,15,16. This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

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Single-chip microprocessor that communicates directly using light

Disclosed is a touch screen panel including a plurality of separate sensing electrodes, and a plurality of separate driving electrodes. Each of the sensing electrodes includes a main electrode and a plurality of expanded parts. Each of the expanded parts includes a sub-electrode extending from the main electrode and at least one expanded electrode extending from the sub-electrode. Each of the driving electrodes surrounds at least part of a corresponding one of the expanded parts.

Touch screen panel

A proximity sensor system includes a sensor matrix array having a characteristic capacitance between horizontal and vertical conductors connected to sensor pads. The capacitance changes as a function of the proximity of an object or objects to the sensor matrix. The change in capacitance of each node in both the X and Y directions of the matrix due to the approach of an object is converted to a set of voltages in the X and Y directions. These voltages are processed by analog circuitry to develop electrical signals representative of the centroid of the profile of the object, i.e, its position in the X and Y dimensions. The profile of position may also be integrated to provide Z-axis (pressure) information.

Object position detector

A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.

Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs

An improved stylus detection system for use on the surface of a display device. An overlay having horizontal and vertical transparent conductors is coupled to other elements of the systems through a bus having a minimal number of bus wires. A control processor issues command signal which selectively couple transparent conductors to a radiative measuring device to determine stylus position accurately. The system includes a radiative pickup stylus having a spherical antenna which receive the overlay signal independent of the angle at which it is held. Further, a contact detecting mode has been added to eliminate spurious contact position measured between strokes, when the stylus is proximate to but not in contact with the overlay.

Stylus sensing system

An architecture is disclosed for improved tilt detection for a radiative pickup stylus. The architecture includes a contact sensing mechanism and a coaxial conductor assembly which provides both position measurement and tilt sensing measurement features. By using the contact sensor to establish a calibration for the position and tilt detection elements, an improved, highly accurate position and tilt sensing capability is provided for radiative pickup stylus for a digitizing display.

Stylus tilt detection apparatus for communication with a remote digitizing display

A method of and service for optimizing an integrated circuit design to improve manufacturing yield. The invention uses manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The invention further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

IC layout optimization to improve yield

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

Michael S. Gray

Papers

Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs

Stylus sensing system

Stylus tilt detection apparatus for communication with a remote digitizing display

IC layout optimization to improve yield

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI