A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.

Semiconductor package and method of manufacturing the same

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

3DIC stacking device and method of manufacture

An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

3D semiconductor device and structure

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Package-on-package assembly with wire bond vias

Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

A method and a system for attaching semiconductor components to a substrate are provided. In the illustrative embodiment the substrate is a leadframe, and the components are semiconductor dice or packages contained on a component substrate such as a wafer. The method includes the steps of holding and dicing the component substrate using a radiation sensitive tape. The method also includes the steps of providing a component attach system having a radiation curing system, and then performing local curing of the dicing tape during a component attach step using the component attach system. The system includes the component attach system which includes a stepper mechanism for stepping the component substrate, and a component attach mechanism having an ejector pin for pushing the components one at a time from the tape and a pick and place mechanism for placing the components on the substrate. The component attach mechanism also includes a housing having a contact surface for physically engaging the dicing tape, and an opening having an outline matching that of a singulated component.

Method for attaching semiconductor components to a substrate using local UV curing of dicing tape

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods

Stenciling machines and methods for forming solder balls on microelectronic workpieces are disclosed herein. In one embodiment, a method for depositing and reflowing solder paste on a microelectronic workpiece having a plurality of dies includes positioning a stencil having a plurality of apertures at least proximate to the workpiece. The method further includes placing discrete masses of solder paste into the apertures and reflowing the discrete masses of solder paste while the stencil is positioned at least proximate to the workpiece and while the discrete masses are in the apertures. In another embodiment of the invention, a stenciling machine for depositing and reflowing solder paste on the microelectronic workpiece includes a heater for reflowing the solder paste, a stencil having a plurality of apertures, and a controller operatively coupled to the heater and the stencil. The controller has a computer-readable medium containing instructions to perform the above-mentioned method.

Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece

Methods for forming semiconductor device packages include applying a photoimageable dielectric adhesive material to a major surface of a semiconductor die and at least partially over conductive elements on the semiconductor die. The photoimageable dielectric adhesive material may be removed from over the conductive elements. The conductive elements are aligned with and bonded to bond pads of a substrate, and the semiconductor die and the substrate are adhered with the photoimageable dielectric adhesive material. A semiconductor device package includes at least one semiconductor die including conductive structures thereon, a substrate including bond pads thereon that are physically and electrically connected to the conductive structures, and a developed photoimageable dielectric adhesive material disposed between the semiconductor die and the substrate around and between adjacent conductive structures.

Michel Koopmans

Papers

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Method for attaching semiconductor components to a substrate using local UV curing of dicing tape

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods

Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece

Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages