M
Michihiro Koibuchi
Researcher at National Institute of Informatics
Publications - 207
Citations - 2247
Michihiro Koibuchi is an academic researcher from National Institute of Informatics. The author has contributed to research in topics: Network topology & Router. The author has an hindex of 22, co-authored 194 publications receiving 2057 citations. Previous affiliations of Michihiro Koibuchi include Graduate University for Advanced Studies & Polytechnic University of Valencia.
Papers
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Proceedings ArticleDOI
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
TL;DR: Evaluation results show that, for a 2-D mesh wormhole NoC, only 12.6% additional hardware resources are needed to implement the proposed DBP mechanism in order to provide graceful performance degradation without chip-wide failure as the number of faults increases to the maximum needed to form ring.
Journal ArticleDOI
A case for random shortcut topologies for HPC interconnects
TL;DR: Using flit-level discrete event simulation, the use of random shortcut topologies, which are generated by augmenting classical topologies with random links, achieve throughput comparable to and latency lower than that of existing non-random topologies such as hypercubes and tori.
Journal ArticleDOI
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms
Jose Flich,Tor Skeie,A. Mejia,Olav Lysne,Pedro López,Antonio Robles,José Duato,Michihiro Koibuchi,Tomas Rokicki,Jose Carlos Sancho +9 more
TL;DR: This paper presents a comprehensive overview of the known topology-agnostic routing algorithms, classify these algorithms by their most important properties, and evaluate them consistently, providing significant insight into the algorithms and their appropriateness for different on- and off-chip environments.
Proceedings ArticleDOI
Prediction router: Yet another low latency on-chip router architecture
TL;DR: This paper proposes a low-latency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration in the prediction routers, and analyzes the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees.
Proceedings ArticleDOI
Run-time power gating of on-chip routers using look-ahead routing
TL;DR: A sleep control method based on look-ahead routing that detects the arrival of packets two hops ahead so as to hide the wake-up delay and reduce the short-term sleeps of channels is proposed.