From the Publisher:
This book presents a unified theory of Generalized Stochastic Petri Nets (GSPNs) together with a set of illustrative examples from different application fields. The continuing success of GSPNs and the increasing interest in using them as a modelling paradigm for the quantitative analysis of distributed systems suggested the preparation of this volume with the intent of providing newcomers to the field with a useful tool for their first approach. Readers will find a clear and informal explanation of the concepts followed by formal definitions when necessary or helpful. The largest section of the book however is devoted to showing how this methodology can be applied in a range of domains.

Modelling with Generalized Stochastic Petri Nets

This chapter is to provide a tutorial and pointers to results and related work on timed automata with a focus on semantical and algorithmic aspects of verification tools. We present the concrete and abstract semantics of timed automata (based on transition rules, regions and zones), decision problems, and algorithms for verification. A detailed description on DBM (Difference Bound Matrices) is included, which is the central data structure behind several verification tools for timed systems. As an example, we give a brief introduction to the tool Uppaal.

/pdf/timed-automata-semantics-algorithms-and-tools-16plqtljps.pdf

Timed Automata: Semantics, Algorithms and Tools

Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it (1) generates another PN or STG which is simpler than the original description and (2) produces an optimized net-list of an asynchronous controller in the target gate library while preserving the specified input-output behavior. An ability of back-annotating to the specification level helps the designer to control the design process. For transforming a specification petrify performs a token flow analysis of the initial PN and produces a transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfill the conditions required to obtain a safe irredundant PN. For synthesis of an asynchronous circuit petrify performs state assignment by solving the Complete State Coding problem. State assignment is coupled with logic minimization and speed-independent technology mapping to a target library. The final net-list is guaranteed to be speed-independent, i.e., hazard-free under any distribution of gate delays and multiple input changes satisfying the initial specification. The tool has been used for synthesis of PNs and PNs composition, synthesis and re-synthesis of asynchronous controllers and can be also applied in areas related with the analysis of concurrent programs. This paper provides an overview of petrify and the theory behind its main functions.

https://eprints.ncl.ac.uk/file_store/production/223989/E9C1DA68-4265-427D-B262-616AF79039D9.pdf

Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers

This paper describes a Petri net model, called Coloured Petri nets (CP-nets), where information is attached to each token. The information can be inspected and modified when a transition fires. For most applications, this generalization of ordinary Petri nets allows the user to make more manageable descriptions, due to the fact that equal subnets can be folded into each other, yielding a much smaller net. The paper investigates how to analyse Coloured Petri nets. It turns out that place-invariants and reachability trees, two of the most important methods for ordinary Petri nets, can be generalized to apply for Coloured Petri nets.

Coloured Petri Nets

The intelligent distributed file system enables the storing of file data among a plurality of smart storage units which are accessed as a single file system. The intelligent distributed file system utilizes a metadata data structure to track and manage detailed information about each file, including, for example, the device and block locations of the file's data blocks, to permit different levels of replication and/or redundancy within a single file system, to facilitate the change of redundancy parameters, to provide high-level protection for metadata, to replicate and move data in real-time, and so forth.

Systems and methods for providing a distributed file system utilizing metadata to track information about data stored throughout the system

A method for operating a server on a computer network to supply data stored on the server in response to requests received on the network. The server stores the requests in a queue and determines a priority value for the request. The priority value includes the sum of a counter value and a cost value, the cost value being monotonically related to the quantity of server resources needed to service the request. When the server selects one of the requests stored in the queue for servicing it picks the request having the lowest priority value of the requests stored in the queue. The selected request is removed from the queue and the counter value is incremented by a value proportional to the cost value associated with the request selected for servicing. In one embodiment, the cost value is proportional to the length of a file specified in the received request. In one embodiment, one of the received requests also includes information specifying a class for the request. The server also determines a maximum priority value for that class, the maximum priority value being at least as great as the priority value having the highest value for any request of that class currently stored in the queue. The server compares the determined priority value for the received request with the maximum priority value and changes the determined priority value to a value greater than the maximum value if the determined priority value was less than or equal to the maximum priority value.

Scheduling server requests to decrease response time and increase server throughput

Most standard cluster interconnect technologies are flexible with respect to network topology. This has spawned a substantial amount of research on topology-agnostic routing algorithms, which make no assumption about the network structure, thus providing the flexibility needed to route on irregular networks. Actually, such an irregularity should be often interpreted as minor modifications of some regular interconnection pattern, such as those induced by faults. In fact, topology-agnostic routing algorithms are also becoming increasingly useful for networks on chip (NoCs), where faults may make the preferred 2D mesh topology irregular. Existing topology-agnostic routing algorithms were developed for varying purposes, giving them different and not always comparable properties. Details are scattered among many papers, each with distinct conditions, making comparison difficult. This paper presents a comprehensive overview of the known topology-agnostic routing algorithms. We classify these algorithms by their most important properties, and evaluate them consistently. This provides significant insight into the algorithms and their appropriateness for different on- and off-chip environments.

A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms

The present invention provides a method and an apparatus for addressing a main memory unit in a computer system which results in improved page hit rate and reduced memory latency by only keeping open some recently used pages and speculatively closing the rest of the pages in the main memory unit. In a computer system with 64 banks and 2 CPUs, only 8 banks may be kept open and the remaining 56 banks are kept closed. Keeping only 8 banks open will not reduce the page hit frequency significantly, but will allow most accesses that are not page hits to access banks that are already closed, so that they are not slowed down by open banks. Thus, the page hit rate is increased and the miss rate is reduced.

Method and computer system for speculatively closing pages in memory

A computer-aided circuit design tool can be described as a set of algorithms applied to an internal representation of a circuit design or specification in order to answer specific questions or perform certain operations. The representation directly limits the operations that can be performed as well as the accuracy of the resulting answers. This dissertation concerns the development and exploration of one such design representation and shows how it is appropriate for a wide range of circuit design tasks. Along the way, we discover some new techniques for specification, modeling, simulation, and verification of circuits. We especially consider real-time aspects of circuit behavior, and we present some significant enhancements to existing real-time verification algorithms.
We present a rich and expressive formalism, called orbital nets, that precisely describes control, timing, and data flow aspects of circuit behavior. We develop the concepts of synchronization, composition, and receptiveness for this formalism, and illustrate how it can be used to specify, model, simulate, and verify digital circuits.
We present a textual description language that provides convenient access to orbital nets through parameterization, partial evaluation, and structural and functional decomposition.
We present efficient hierarchical real-time simulation and verification algorithms. We prove the equivalence of continuous time and discrete time semantics for orbital nets, and develop some new geometric timing algorithms that exploit concurrency to efficiently verify real-time safety properties.

Representing and modeling digital circuits

A main memory indexing scheme optimizes consecutive page hits in computer systems having a main memory system and a cache memory. In accordance with the present invention, one or more bank select bits required by the main memory system are formed from one or more of the address bits that are used by the cache memory as the tag field. Preferably, the lower-order bits of the tag field are used. To increase the page hit rate even further, additional bank select bits are formed from the address bits immediately above the bits used to access columns. In one embodiment of the present invention, address bits are simply mapped to bank bits using a one-to-one correspondence. In another embodiment, address bits from the tag field and address bits immediately above the column bits are combined using a function such as an exclusive-OR operation or an addition operation, with the result of the function provided to the bank select bits. The present invention greatly improves the page hit rate of computer systems, while requiring few additional resources.

Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization

Tomas Rokicki

Papers

Scheduling server requests to decrease response time and increase server throughput

A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms

Method and computer system for speculatively closing pages in memory

Representing and modeling digital circuits

Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization