M
Mika Nyström
Researcher at California Institute of Technology
Publications - 15
Citations - 1061
Mika Nyström is an academic researcher from California Institute of Technology. The author has contributed to research in topics: Asynchronous communication & Asynchronous system. The author has an hindex of 12, co-authored 15 publications receiving 1040 citations.
Papers
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Proceedings ArticleDOI
The design of an asynchronous MIPS R3000 microprocessor
Alain J. Martin,Andrew M. Lines,Rajit Manohar,Mika Nyström,Paul I. Pénzes,R. Southworth,Uri Cummings,Tak Kwan Lee +7 more
TL;DR: The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput.
Journal ArticleDOI
Asynchronous Techniques for System-on-Chip Design
Alain J. Martin,Mika Nyström +1 more
TL;DR: The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree, and basic building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization.
Book ChapterDOI
ET 2 : a metric for time and energy efficiency of computation
TL;DR: An efficiency metric for VLSI computation that includes energy is investigated and an approximation for Etn (for arbitrary n) of an optimally sized system that can be computed without actually sizing the transistors is derived; it is proved that when multiple, adjustable supply voltages are allowed, the optimal Et2 for the sequential composition of components is achieved when the supply voltage is adjusted so that the components consume equal power.
Proceedings ArticleDOI
The Lutonium: a sub-nanojoule asynchronous 8051 microcontroller
Alain J. Martin,Mika Nyström,Papadantonakis Karl S,Paul I. Pénzes,P. Prakash,Catherine G. Wong,Jonathan Chang,K.S. Ko,Benjamin N. Lee,E. Ou,Jim Pugh,Eino-Ville Talvala,J.T. Tong,Andrea Tura +13 more
TL;DR: The structure of a fine-grain pipeline optimized for Et/sup 2/ efficiency, some of the peripherals implementation, and the advantages of an asynchronous implementation of a deep-sleep mechanism are described.
Journal ArticleDOI
Three generations of asynchronous microprocessors
TL;DR: This work traces the evolution of Caltech asynchronous processors from a simple proof of concept, to a high-performance MIPS-like processor using a different buffer circuit for better performance, to the latest 8051 clone targeting low-energy operation.