An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array, comprises a large number (e.g. 16,384 in a 128×128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered, parallel data, including spatial translation by shifting or "sliding" of bits vertically or horizontally to neighboring processing elements.

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Massively parallel processor computer

A knee arthroplasty prosthesis includes a femoral component having multiple pieces with engagement means provided for engaging various pieces of the femoral component to one another following their insertion in the incised area of the femur. A tibial component includes multiple pieces designed for assembly following positioning in the incision. The tibial component includes a Morse taper cavity on one piece of the tibial component and a Morse taper extension on another member of the component for receipt therein.

Knee arthroplasty prosthesis and method

A novel parallel-prefix architecture for high speed module 2/sup n/-1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures.

High-speed parallel-prefix module 2/sup n/-1 adders

A knee joint prosthesis includes a femoral component, a tibial plateau, and a tibial bearing member. The design and geometry of the articulation surfaces of the condylar elements of the femoral component and tibial bearing member is such that contact area between the articulation surfaces is maximized during flexion of the prosthesis. This is achieved by increasing the coronal radius of the bearing surfaces of the femoral component in the anterior to posterior direction along the bearing surface, i.e., increasing the coronal radius of the bearing surfaces of the femoral component as the femoral component transitions from extension to flexion.

Femoral component condyle design for knee prosthesis

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

An arithmetic logic array employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal data. Two 4-bit data inputs are received along with a 5-bit Op code, a carry input, and decimal arithmetic operation signals. In response to a decimal add (DA) one data input is increased by a count of six, and in response to either a BCD add or a BCD subtract (DA + DS) the output is decreased by a count of six if no carry output is generated.

Current mode binary/bcd arithmetic array

A carry look-ahead array is used with up to six 4 bit binary arithmetic/logic arrays to expeditiously process 24 bit binary data. Advantageously, two carry look-ahead arrays may be used in combination for processing 44 bit data, and seven carry lookahead arrays may be used for processing 144 bit data. Soft saturating current mode circuit elements are employed which provide an output voltage swing between 0 volt and -0.5 volt.

Current mode carry look-ahead array

An arithmetic logic array employing soft-saturating current mode logic gates receives two binary input signals and a binary operation mode signal and includes a half-adder and logic function portion for generating half-sums of the input signals and carry generate signals, a carry look-ahead portion for generating carrys in response to half-sum and carry generate inputs, and a portion for combining the half-sums and carrys to produce a resultant binary output. Another portion may be included to produce carry generate and propagate signals useful with a separate look-ahead carry array.

Current mode arithmetic logic array

A magnitude comparison circuit compares two X-bit binary numbers and two Y-bit binary numbers when a mode control signal is in a first condition and generates outputs indicating the relative magnitudes of the X-bit binary numbers and the Y-bit binary numbers. The magnitude comparison circuit compares two Z-bit binary numbers when the mode control signal is in a second condition and generates an output indicating the relative magnitude of the Z-bit binary numbers, where Z equals the sum of X and Y.

Magnitude comparison circuit

A 5-bit D-type master/slave counter/shift register with buffered outputs is disclosed. The counter implements the load, count up, count down, and reset functions and also has the capability to be reconfigured into an inverting serial shift register for Non-Functional Test (NFT) techniques. In addition, the fifth bit may optionally be removed from the counter logic and used as a parity bit, although it will be necessary to use some external logic to implement this parity function.

Miller Homer W

Papers

Current mode binary/bcd arithmetic array

Current mode carry look-ahead array

Current mode arithmetic logic array

Magnitude comparison circuit

5-Bit counter/shift register utilizing current mode logic