Patent
Magnitude comparison circuit
TLDR
In this paper, a magnitude comparison circuit was proposed to compare two X-bit binary numbers and two Y-bit numbers when a mode control signal is in a first condition and generates outputs indicating the relative magnitudes of the X-bits binary numbers.Abstract:
A magnitude comparison circuit compares two X-bit binary numbers and two Y-bit binary numbers when a mode control signal is in a first condition and generates outputs indicating the relative magnitudes of the X-bit binary numbers and the Y-bit binary numbers. The magnitude comparison circuit compares two Z-bit binary numbers when the mode control signal is in a second condition and generates an output indicating the relative magnitude of the Z-bit binary numbers, where Z equals the sum of X and Y.read more
Citations
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Patent
Circuit for comparing a plurality of binary inputs
TL;DR: A circuit for comparing a plurality of binary numbers according to this invention includes a circuit (101, 102, 103, 111) for receiving M (M ≧ 3) binary numbers (A, B, C) and generating and outputting a signal (NA, NB, NC) representing which of the binary numbers is maximum or minimum as mentioned in this paper.
Patent
Cache memory system, and comparator and MOS analog XOR amplifier for use in the system
Sheau-Jiung Lee,Gene Yang +1 more
TL;DR: The MOS analog comparator provided in this article comprises N number of MOS analogue XOR means for performing the digital XOR function and a MOS Analog NOR mean for performing digital NOR function.
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Apparatus for converting numeral representing data coding formats received or derived by a central processing unit
TL;DR: In this paper, a central processing unit (CPCU) is converted between data coding formats employed externally and internally of a CPU of a data processing system by a treatment internal to the CPU.
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Arithmetic unit with alternate mark inversion (AMI) coding
Harufusa Kondo,Hideki Ando +1 more
TL;DR: In this paper, an arithmetic unit with true and false deciding circuits (21 to 24) and an AND gate (50) was introduced to output AMI codes of the first input signal A and the second input signal B in response to the sign (most significant bit value) of the second signal B. The arithmetic unit thus outputs the AMI code of A having the output of the AND gate as a high order bit and the most significant bit F 4 of the output F of the adder as a low order bit.
References
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Patent
Serial bit comparator with selectable bases of comparison
TL;DR: In this paper, a serial by bit comparator device is disclosed for determining the relative magnitude of two binary numbers, and means are provided to sense in which of the storage means there still remains an interrogating bit, hence determining which proposition is true or false.
Patent
Multi digit verification apparatus and method
TL;DR: In this article, an operator enters the characters of the identification code into the apparatus by a suitable device, such as a keyboard, and the entered identification code is compared for verification by a predetermined relationship among the characters.