The 3-D integration using through silicon vias (TSVs) is one of the most promising approaches to overcome the interconnect delay problem of current CMOS technologies. Nevertheless, the TSV energy consumption is not negligible due to the high capacitive coupling. This paper presents an abstract and yet accurate model to estimate the pattern-dependent energy consumption in arrays of TSVs; it is the first high-level model including the effects of the voltage-dependent metal–oxide–semiconductor (MOS) capacitances surrounding each TSV and a possible temporal misalignment between the input signals. We propose a regression method to estimate the dynamic size of the coupling capacitances as a function of the bit probabilities. Experimental results for real and synthetic data streams, a submicrometer 9-bit TSV array and a 65-nm technology show that the presented TSV energy model exhibits a maximum error of 5.53%, while the traditional high-level model shows errors of up to 79.77%. Furthermore, the new insights provided by our model reveal a possibility to easily boost the efficiency of existing low-power codes for TSV structures by over 10% without affecting the coding efficiency for the planar metal wires or the encoder complexity.

High-Level Energy Estimation for Submicrometric TSV Arrays

Edge effects on the TSV array capacitances and their performance influence

3D integration is one of the most promising solutions for the scaling of future integrated circuits (ICs). Nevertheless, the 2D metal wires and 3D through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs, due to their high capacitive crosstalk, which can be reduced by a coding approach. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV arrays. Additionally, these 3D CACs do not reduce the metal wire crosstalk. This work presents a crosstalk avoidance approach for 3D ICs which overcomes both limitations. The method remaps the bits of existing 2D CACs onto a TSV array in a way that results in the minimum possible TSV crosstalk. Experimental results, obtained by circuit simulations in combination with an electromagnetic field solver, show that the presented technique can reduce the crosstalk of TSVs and metal wires by about 30 % and 50 %, respectively. In comparison, with higher hardware costs, existing 3D CACs only reduce the TSV crosstalk by a maximum of 11.45 %, while providing no optimization of the metal wire crosstalk.

Edge effect aware crosstalk avoidance technique for 3D integration

Through-silicon vias (TSVs) is one of the key enabling technologies of 3-D ICs. However, the crosstalk problem among the adjacent TSVs decreases the performance and deteriorates the signal integrity of TSV bus. This paper proposes an exhaustive search technique of 6C crosstalk avoidance codewords that is applicable for TSV arrays of different sizes to suppress the crosstalk noise below 6C level. The proposed technique has lower system overhead than that of 3D 4-LAT and 6CmFNS methods.

An exhaustive search of the 6C level crosstalk avoidance codes for TSV array

Hexagonal ground-shielding through silicon vias (TSVs) in 3D ICs are explored based on measurement and simulation. The measured S-parameters of the TSV-bundle part are successfully extracted by de-embedding technique. The results math well with simulations up to 20GHz. The proposed TSV bundle has a good performance of return and insertion loss. For the hexagonal ground TSV shield system, the crosstalk analysis of neighbor signals in the TSV shield system is made based on the measurements and simulations. The electronic and magnetic field plots show a good capacitive and inductive coupling isolation for the victim signal TSV with shielding ground TSVs. Compared to those coupled-TSVs systems without ground guide, the ground-shielding TSV as well as coaxial TSV has higher noise over the range of frequencies.

Measurement and Crosstalk Analysis of Hexagonal TSV Bundle in 3D ICs

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a $3 \times 3$ TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.

Min Miao

Papers

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias