Microelectromechanical systems (MEMS) have been familiar in the field of microelectronics and device technology since 1965, when Harvey C. Nathanson invented the first MEMS device (known as the resonant gate transistor). Since that time, MEMS have represented a prominent field for academic research, with simplified implementations of several devices such as sensors, transducers, actuators, and accelerometers being fabricated. According to MEMS technology, all devices could be fabricated using standard integrated circuit (IC) techniques, with the device?s lateral dimensions normally ranging from a maximum of 500 nm to submicron ranges.

Paradigm Phase Shift: RF MEMS Phase Shifters: An Overview

This paper presents the design and fabrication of a micro Pirani gauge using VO x as the sensitive material for monitoring the pressure inside a hermetical package for micro bolometer focal plane arrays (FPAs). The designed Pirani gauge working in heat dissipating mode was intentionally fabricated using standard MEMS processing which is highly compatible with the FPAs fabrication. The functional layer of the micro Pirani gauge is a VO x thin film designed as a 100 × 200 μm pixel, suspended 2 μm above the substrate. By modeling of rarefied gas heat conduction using the Extended Fourier’s law, finite element analysis is used to investigate the sensitivity of the pressure gauge. Also the thermal interactions between the micro Pirani gauge and bolometer FPAs are verified. From the fabricated prototype, the measured device TCR is about −0.8% K−1 and the sensitivity about 1.84 × 10−3 W K−1 mbar−1.

Integrated micro Pirani gauge based hermetical package monitoring for uncooled VO x bolometer FPAs

A vacuum-encapsulated silicon switch with a curved electrode is characterized for operation in harsh environments. An ultraclean vacuum encapsulation process (episeal) seals the switch after release, providing a pristine operating environment for switching operations. In these devices, the curved beam of the actuator enhances the overdrive voltage tolerance to be more than 100 V. The ON/OFF cycle tests were carried out up to 10
 5
 cycles at room temperature, and at least 10
 4
 cycles under an elevated temperature of 300°C. Throughout the 300°C tests, an average contact resistance of ~ 28 kΩ is measured, demonstrating the stability of the contact. Finally, high speed pulse I-V monitoring unit was used to observe 13-μs switching speed.

Fabrication and Characterization of a Vacuum Encapsulated Curved Beam Switch for Harsh Environment Application

The 3-D integration using through silicon vias (TSVs) is one of the most promising approaches to overcome the interconnect delay problem of current CMOS technologies. Nevertheless, the TSV energy consumption is not negligible due to the high capacitive coupling. This paper presents an abstract and yet accurate model to estimate the pattern-dependent energy consumption in arrays of TSVs; it is the first high-level model including the effects of the voltage-dependent metal–oxide–semiconductor (MOS) capacitances surrounding each TSV and a possible temporal misalignment between the input signals. We propose a regression method to estimate the dynamic size of the coupling capacitances as a function of the bit probabilities. Experimental results for real and synthetic data streams, a submicrometer 9-bit TSV array and a 65-nm technology show that the presented TSV energy model exhibits a maximum error of 5.53%, while the traditional high-level model shows errors of up to 79.77%. Furthermore, the new insights provided by our model reveal a possibility to easily boost the efficiency of existing low-power codes for TSV structures by over 10% without affecting the coding efficiency for the planar metal wires or the encoder complexity.

High-Level Energy Estimation for Submicrometric TSV Arrays

Wafer level bonding is widely applied in the manufacture of sensors, actuators and CMOS MEMS. Bonding technology includes direct bonding, anodic bonding, eutectic bonding, adhesive bonding and glass frit bonding. Glass frit bonding has pattern-able, excellent sealing performances, high bonding strength, don't need apply any voltage during bonding process and less CTE mismatch compared to glass and silicon is more suitable for the hermetic MEMS packages such as gyroscope, accelerometer and RF resonator. To ensure the performances and reliability of assembled parts, the mainly processes both screen printing process and wafer-to-wafer bonding process have to be properly controlled. The limited line width of screen printed glass frit and the optimized bonding conditions of wafer level glass frit bonding process for accelerometer were investigated in this study. Five different line width in a stencil have been designed for confirming the limitation of line width for glass frit screen printing process. To ensure the affect of bonding conditions on sealing performance and bonding strength, a series both of bonding force and temperature for wafer-to-wafer thermal compression bonding were been chosen under reasonable range. Also, the effect of additional ball pin applied during bonding process has been discussed. The bonding performances and reliability were carried out by die shear test and Helium leak test according to the MIL standard 883E 1014.9. The results indicated that the MEMS packaging yield mainly controlled by screen printing process and the finest line width of glass frit is 100 um and 150 um after screen printing and bonding process respectively, when the packaging yield more than 95% can be achieved. The final thickness of glass frit after bonding has been controlled to 10 um for best sealing performance. The bonding temperature is more effective than bonding force both on packaging yield and sealing performance. At the same time, the results shown that applied ball pin on the glass wafer induced the crack occurrence on the center of upper glass wafer during bonding process. From the results of die shear test and Helium leak test, under the optimized bonding conditions, the average bonding strength is up to 36 MPa and the Helium leak value is about 10−9 atm cc/ sec far smaller than the standard value (108 atm cc/ sec). From the fracture analysis after die shear testing, the fracture occurred on the silicon wafer, which reveals that the bonding strength of interface between glass and wafer is strong enough. These results are useful for employing new bonding designs lead to better reliability and performance for wafer level MEMS package.

Wafer level glass frit bonding for MEMS hermetic packaging

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a $3 \times 3$ TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

Many MEMS (micro electro-mechanic systems) parts have to meet the requirements for vacuum packaging. In vacuum packaging, leakage and gas permeation, which affects the normal function of the components, are major problems. Hermetic sealing is one of the most important technologies for reliable vacuum packaging. In this paper, several hermetic sealing technologies for vacuum packaging was presented, including eutectic bonding, adhesive bonding, glass frit bonding, and silicon-glass anodic bonding. Furthermore, the author introduced two approaches to deal with sealing imperfect surface caused by electric feedthroughs, which link to the outside of the small cavity of MEMS sensors. The getter was discussed as it is essential to keep the vacuum environment inside the cavity of device since the inner walls might release gas after hermetic seal

MEMS Vacuum Packaging Technology and Applications

Applications of dry film photoresists in MEMS (micro-electro-mechanical systems) products are expected, since dry film photoresists have numerous advantages such as easily to be laminated and removed after processing. This paper reports on the process study of fabricating microstructures using commercially available dry film photoresists. Single layer and multi-lever laminations were performed; lateral resolutions of patterned trenches, and sidewall verticality were investigated. Trenches of 12 m wide were successfully patterned and sidewalls with 90 /-I verticality were achieved. Furthermore, dry film photoresists were laminated successfully on a nonplanar wafer with previously etched V-grooves for the next-step fabrication. The results demonstrated new possibilities of dry film photoresist for MEMS applications.

Process development of negative tone dry film photoresist for MEMS applications

Through silicon via(TSV) is the most vital technology of the advanced 3D system-in-package integration and 3D IC integration.The insulation integrity of TSVs is among the key factors that determine TSV electrical properties and long term reliability.Total production cost can be reduced by performing in-line test during manufacturing and then screening out defective wafers at early stage.An in-line method is proposed to verify the TSV insulation quality after the blind vias are formed and before next process(i.e.wafer thinning) is carried out.During the test,the leakage current data between two blind vias is obtained and plotted through I-V characteristic test by probing the pads upon these blind TSVs.TSVs can be determined as a qualified one with insulation integrity when I-V curve varies linearly between 7 V～10 V and the leakage current is on the orders of dozens of pA.If an abrupt rise of leakage current or even breakthrough appears at voltages equal to or under 7 V,then it can be deduced that the insulation integrity of one or both of the blind vias under test has been compromised.Finite element method(FEM) simulation was used to illustrate the testing principle,and experimental test were carried out for validation.

An In-line Test Method for the TSV Insulation Integrity

This paper reports a novel microelectromechanical systems(MEMS)device—Micromechined Pirani Gauge—which is used to monitor pressure changes in vacuum package.This Pirani Gauge utilizes heat conduct in a small gap between the silicon heater and heat sinks to monitor pressure.A lateral micromachined Pirani Gauge with a simplified structure was designed and prepared using dissolved wafer process and bonding technology.The experiment results show our lateral micromachined Pirani Gauge has a very good linearity of thermal impedance versus pressure in the range of 10 Pa ~ 300 Pa.

Jin Yufeng

Papers

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

MEMS Vacuum Packaging Technology and Applications

Process development of negative tone dry film photoresist for MEMS applications

An In-line Test Method for the TSV Insulation Integrity

Research on Micromachined Pirani Gauge