An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by ionizing radiation exposure have diminished by aggressive semiconductor scaling, the question remains whether there may be unknown, potentially worse threats lurking in the deep submicron regime. This manuscript provides a basic overview of some of the materials, devices, and designs that are being explored or, in some cases, used today. An overview of radiation threats and how radiation effects can be characterized is also presented. Last, the paper provides a detailed discussion of what we know now about how modern devices and materials respond to radiation and how we may assess, through the use of advanced analysis and modeling techniques, the relative hardness of future technologies

Total-Ionizing-Dose Effects in Modern CMOS Technologies

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A single-transistor latch phenomenon observed in silicon-on-insulator (SOI) MOSFETs is reported This latch effect, which occurs at high drain biases, is an extreme case of floating-body effects which are present in SOI MOSFETs The floating body results in positive feedback between the impact ionization current, body-to-source diode forward bias, and transistor currents At large drain voltages, this positive feedback can maintain a high-drain-to-source current even when the MOS gate is biased well below its threshold voltage >

Single-transistor latch in SOI MOSFETs

A new way of making sidewall channel stops for silicon on insulator devices (including silicon on oxide, silicon on nitride, and silicon on sapphire devices). While the moat regions 11, 13 (where the active devices will be formed) are covered by thick masking material 24, a high energy implantation step introduces additional doping into exposed silicon regions 14'. Before the mesa etch is performed to isolate the individual active device regions 32 a filament 28 is formed on the walls of the masking material 24 which covers the predetermined locations of the active device regions 32. The mesa etch is then performed using a chemistry which will be blocked not only by the original masking material 24 but also by the sidewall filaments 28. Thus, the doping level defined by implantation into regions 14' will extend into the sidewalls of the mesas 32 for a distance which is controlled not only by the lateral diffusion length of those dopants, but also by the thickness of the sidewall filament 28.

Sidewall channel stop process

A transistor and a method of making a transistor are disclosed, where a tunnel diode is formed to make connection between the source of the transistor and the body node underlying the gate. For the example of an n-channel transistor, a p+ region is formed by implant and diffusion under the n+ source region, the p+ region in contact on one end with the relatively lightly doped p-type body node. The relatively high dopant concentration of both the p+ region and the n+ source region creates a tunnel diode. The tunnel diode conducts with very low forward voltages, which causes the body node region to be substantially biased to the potential of the source region. Methods for forming the transistor are also disclosed, including the use of a source/drain anneal prior to p-type implant, or alternatively a second sidewall oxide filament, to preclude the boron from counterdoping the LDD extension at the source side. Both silicon-on-insulator and bulk embodiments are disclosed.

Silicon-on insulator transistor with internal body node to source node connection

A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

Thin oxide sidewall insulators for silicon-over-insulator transistors

n-channel SOI MOSFETs with floating bodies show a threshold voltage shift and an improvement in subthreshold slope at high drain biases. The magnitude of this effect depends on the device parameters and the starting SOI substrate. A simple device model is presented that explains the observed characteristics to be due to MOS back-bias effects resulting from the positively charged floating body. The improvement in the subthreshold slope is the outcome of positive feedback between the body potential and the transistor channel current. >

Mishel Matloubian

Papers

Single-transistor latch in SOI MOSFETs

Sidewall channel stop process

Silicon-on insulator transistor with internal body node to source node connection

Thin oxide sidewall insulators for silicon-over-insulator transistors

Modeling of the subthreshold characteristics of SOI MOSFETs with floating body