Power is supplied to an information handling system chipset with a single voltage regulator having dual phases A first phase of the voltage regulator provides power to a low power state power rail in an independent mode to support a low power state, such as a suspend or hibernate state A second phase of the voltage regulator provides power to a run power state power rail in combination with the first phase by activation of a switch, such as a MOSFET load switch, that connects the low power state power rail and the run power state power rail Voltage sensed from both power rails is applied to control voltage output so that the run power state power rail is maintained within more precise constraints than the low power state power rail

System and Method for Powering an Information Handling System in Multiple Power States

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

Flash EEPROM System with Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks

A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Semiconductor memory device and method of operating the same

A system includes a computing device that selectively communicates with a self-powered device. The self-powered device has several modes of operation, including a first low-power mode of operation and a second high-power mode of operation. The self-powered device is to communicate with the computing device when the self-powered device is in the second mode of operation. The self-powered device may conserve power by alternating between the first mode of operation and the second mode of operation such that the self-powered device is in the second mode of operation during pre-determined or adaptively-determined time intervals. A duty-cycle of the second mode of operation relative to the first mode of operation may be in accordance with a power budget for the self-powered device.

Self-Powered Devices and Methods

The present invention provides a data processing system wherein the waste of use of each storage area by ECC codes is avoided to improve or increase the number of assurances for rewriting of information stored in a non-volatile memory. A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20 Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can be avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.

Data processing system and data processing method

To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device

A semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory while sharing a data bus, and utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. This volatile memory includes a volatile storage circuit for latching repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. A fuse program circuit is not needed for the defect repair, but a defect which occurs after burn-in can be newly repaired so that the new defect can be repaired even after the packaging is formed over a circuit substrate.

Semiconductor integrated circuit device, memory module and storage device

For an internal circuit having a first operation mode consuming a first operational current and a second operation mode consuming a second and smaller operational current, a first regulator for providing a predefined voltage from an input voltage and having a current supply ability corresponding to the first operational current and a second regulator having a current supply ability corresponding to the second operational current are provided. A power supply control unit operates the first regulator in response to a first control signal instructing the first operation mode and operates the second regulator in response to a second control signal instructing the second operation mode. The internal circuit and power supply control unit are provided in one semiconductor integrated circuit device.

Electronic device having power supply regulators controlled according to operation mode of internal circuit

For an internal circuit having a first operation mode consuming a first operational current and a second operation mode consuming a second operational current, which is smaller than the first operational current, a first power source regulator for stepping down a predefined output power supply voltage from an input power supply voltage and having a current supply ability corresponding to the first operational current of the internal circuit and a second power source gulator having a current supply ability corresponding to the second operational current are combined in order to, under the control of a power supply control unit, operate the first step-down type regulator in response to a first control signal instructing the first operation mode in the internal circuit and to operate the second step-down type regulator in response to a second control signal instructing the second operation mode. In this case, the internal circuit and power supply control unit are provided in one semiconductor integrated circuit device so that reduced power consumption and power supply switching in accordance with the operation mode can be achieved.

Mitsuru Hiraki

Papers

Data processing system and data processing method

Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device

Semiconductor integrated circuit device, memory module and storage device

Electronic device having power supply regulators controlled according to operation mode of internal circuit

Data processing system