생체의 모델링과 Simulation

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Is your memory hierarchy stopping your microprocessor from performing at the high level it should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem. The book tells you everything you need to know about the logical design and operation, physical design and operation, performance characteristics and resulting design trade-offs, and the energy consumption of modern memory hierarchies. You learn how to to tackle the challenging optimization problems that result from the side-effects that can appear at any point in the entire hierarchy.As a result you will be able to design and emulate the entire memory hierarchy. . Understand all levels of the system hierarchy -Xcache, DRAM, and disk. . Evaluate the system-level effects of all design choices. . Model performance and energy consumption for each component in the memory hierarchy.

Memory Systems: Cache, DRAM, Disk

The Monte Carlo method.- Sampling from known distributions.- Pseudorandom number generators.- Variance reduction techniques.- Quasi-Monte Carlo constructions.- Using quasi-Monte Carlo constructions.- Using quasi-Monte Carlo in practice.- Financial applications.- Beyond numerical integration.- Review of algebra.- Error and variance analysis for Halton sequences.- References.- Index.

Monte Carlo and Quasi-Monte Carlo Sampling

Static-timing analysis (STA) has been one of the most pervasive and successful analysis engines in the design of digital circuits for the last 20 years. However, in recent years, the in- creased loss of predictability in semiconductor devices has raised concern over the ability of STA to effectively model statistical variations. This has resulted in extensive research in the so-called statistical STA (SSTA), which marks a significant departure from the traditional STA framework. In this paper, we review the recent developments in SSTA. We first discuss its underlying models and assumptions, then survey the major approaches, and close by discussing its remaining key challenges.

Keynote Paper Statistical Timing Analysis: From Basic Principles to State of the Art

Reducing power dissipation is one of the most important issues in very large scale integration design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. Multithreshold technology has emerged as a promising technique to reduce leakage power. This paper presents several heuristic techniques for efficient gate clustering in multithreshold CMOS circuits by modeling the problem via bin-packing (BP) and set-partitioning (SP) techniques. The SP technique takes the circuit's routing complexity into consideration which is critical for deep submicron (DSM) implementations. By applying the techniques to six benchmarks to verify functionality, results obtained indicate that our proposed techniques can achieve on average 84% savings for leakage power and 12% savings for dynamic power. Furthermore, four hybrid clustering techniques that combine the BP and SP techniques to produce a more efficient solution are also devised. Ground bounce was also taken as a design parameter in the optimization problem. While accounting for noise, the proposed hybrid solution achieves on average 9% savings for dynamic power and 72% savings for leakage power dissipation at sufficient speeds and adequate noise margins.

Design and optimization of multithreshold CMOS (MTCMOS) circuits

Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power dissipation. This paper presents two techniques for efficient gate clustering in MTCMOS circuits by modeling the problem via Bin-Packing (BP) and Set-Partitioning (SP) techniques. An automated solution is presented, and both techniques are applied to six benchmarks to verify functionality. Both methodologies offer significant reduction in both dynamic and leakage power over previous techniques during the active and standby modes respectively. Furthermore, the SP technique takes the circuit's routing complexity into consideration which is critical for Deep Sub-Micron (DSM) implementations. Sufficient performance is achieved, while significantly reducing the overall sleep transistors' area. Results obtained indicate that our proposed techniques can achieve on average 90% savings for leakage power and 15% savings for dynamic power.

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Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic.

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.

MOS current mode circuits: analysis, design, and variability

A new high-speed domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.

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Mohab Anis

Papers

Design and optimization of multithreshold CMOS (MTCMOS) circuits

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

MOS current mode circuits: analysis, design, and variability

High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies