A full color three electrode surface discharge type plasma display device that has fine image elements and is large and has a bright display. The three primary color luminescent areas are arranged in the extending direction of the display electrode pairs in a successive manner and an image element is composed by the three unit luminescent areas defined by these three luminescent areas and address electrodes intersecting these three luminescent areas. Further, phosphors are coated not only on a substrate but also on the side walls of the barriers and on address electrodes. The manufacturing processes and operation methods of the above constructions are also disclosed.

Full color surface discharge type plasma display device

Disclosed is a method for driving a plasma display panel in which a plurality of first electrodes and second electrodes are arranged parallel to each other, a plurality of third electrodes are arranged to cross the first and second electrodes, and discharge cells defined with areas in which the electrodes cross mutually are arranged in the form of a matrix According to the driving method, a reset period is a period during which the distribution of wall charges in the plurality of discharge cells is uniformed An addressing period is a period during which wall charges are produced in the discharge cells according to display data A sustain discharge period is a period during which sustain discharge is induced in the discharge cells in which wall charges are produced during the addressing period The driving method in accordance with the present invention comprises a step of applying a first pulse in which an applied voltage varies with time so as to induce first discharge in the lines defined by the first and second electrodes, and a step of applying a second pulse in which an applied voltage varies with time so as to induce second discharge as erase discharge in the lines defined by the first and second electrodes These steps are carried out during the reset period

Method for driving plasma display panel

A plasma display device includes: a dielectric layer on which a plurality of through-holes of a dielectric layer is disposed in a matrix shape; upper and lower electrode layers formed at both upper and lower surfaces of the dielectric layer; upper and lower substrates disposed on the outer surface of the upper and lower electrode layers; and a third electrode layer having a plurality of third electrodes which are formed between the upper substrate and the upper electrode layer, or the lower substrate and the lower electrode layer, and are insulated from the upper and lower electrode layers. Accordingly, a plasma display device can be realized which has stability and efficiency of a micro discharge. In addition, each pixel can concurrently carry out a sustain discharge by applying an alternating voltage to upper and lower electrodes forming sustain electrodes.

Plasma Display Panel

Designation of specific heating zones and increase in minimum resistance relative to prior heaters of the type to which the present invention pertains is achieved, together with flexibility or bendability, if desired, by slotting the outer conductor of the heater. Additional flexibility is also achieved by confining the high mu material only to those regions of the device where heating is desired, the unslotted regions.

Slotted autoregulating heater

A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.

Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells

A multicolor gaseous discharge display device utilizes electroluminescent techniques as a plasma environment. A layer of electroluminescent phosphor material is used as the dielectric layer overlying the conductor electrodes in an A.C. plasma device. In one embodiment for generating a two color display, only one of the dielectric layers uses an electroluminescent phosphor for a two color display. In a second embodiment, both dielectric layers use different electroluminescent material for a three color display. A layer of n-type semiconductor material is required between the conductor electrodes and the phosphor dielectric to reduce the electroluminescent voltage threshold, while a refractory layer is used to protect the phosphor against ion bombardment during discharge of said device.

Color plasma display device

A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200° C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800° C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si x Ge 1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.

Multilevel electronic structures containing copper layer and copper-semiconductor layers

A D.C. gas discharge display panel for operation in a storage mode with internal memory, comprises a gas filled envelope bounded by a pair of glass plates (2 and 3), which carry on their respective internal surfaces orthogonal arrays of cathode conductors (4) and anode conductors (6) separated by a discharge gap (30). The array of cathode conductors is covered by a layer (10) of resistive material, which in turn is covered by a cermet layer (12). The cermet layer protects the cathode conductors from ion bombardment induced sputtering during discharge. The layers provide a resistance to each discharge cell, and provide isolation between individual cathodes by reducing discharge spreading along the cathode conductors and preventing surface charge build-up during panel operation. By using a combination of metal and insulator in the resistance layer, the D.C. discharge can be sustained at lower operating voltage, permitting a reduction in the power requirements of the panel.

D.C. gas discharge display panel with internal memory

Cu (14) is deposited as a film on the surface of a single crystalline semiconductor substrate (18) of Si or Ge, while the substrate is held at room temperature. It has been found that the materials will react by themselves over an extended period of time to form a Cu-silicide (20) or Cu-germanide (46) compound interface. The process may be used to produce interconnection metallization for integrated circuits, but, in the context of existing VLSI processes, heat is used to accelerate the formation using the minimum desirable parameters of a temperature of about 150°C for about 20 minutes. Contrary to the belief in the art that Cu always diffuses in silicon, the resulting interface junction has been found to demonstrate superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800°C) stability Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si x Ge 1-x layer on Si substrate, and the use of an intermediate layer of a refractory metal such as W. Various other VLSI embodiments are also disclosed.

Copper-semiconductor compounds capable of being produced at room temperature

A multi-layer contact process is described for providing contact to a shallow semiconductor region forming a semiconductor PN junction and with a silicon semiconductor body. The multi-layer structure includes a layer of polycrystalline silicon doped with an impurity of the same conductivity type as that of the semiconductor region. A first layer of a refractory alloy is deposited over the polycrystalline silicon layer to provide electrically stable interface therewith. A second layer of another refractory metal or alloy is deposited over the first refractory metal alloy layer and serves to protect the shallow PN junction against current leakage failure. A third layer of interconnect metal is deposited over the multi-layer contact structure. The resulting structure provides a low resistance ohmic contact to a shallow semiconductor region with improved electrical characteristics.

Mohamed Osama Aboelfotoh

Papers

Color plasma display device

Multilevel electronic structures containing copper layer and copper-semiconductor layers

D.C. gas discharge display panel with internal memory

Copper-semiconductor compounds capable of being produced at room temperature

Process for making a contact structure including polysilicon and metal alloys