Mohammad Rahmani Fadiheh

TL;DR: New classes of covert channel attacks which are possible in average-complexity processors with in-order pipelining are presented, as they are mainstream in applications ranging from Internet-of-Things to Autonomous Systems.

TL;DR: A formal method for security verification by HW property checking based on extending Unique Program Execution Checking (UPEC) to out-of-order processors and detects a new, so far unknown vulnerability, called Spectre-STC, indicating that also single-threaded processors can be vulnerable to contention-based Spectre attacks.

TL;DR: This paper modifications SQED by incorporating a symbolic initial state in its BMC-based analysis and generalizes the approach into the S2QED method, which can separate logic bugs from electrical bugs in QED-based postsilicon validation and makes a strong contribution to pre-silicon verification.

TL;DR: In this paper, the authors present new classes of covert channel attacks which are possible in average-complexity processors with in-order pipelining, as they are mainstream in applications ranging from Internet-of-Things to Autonomous Systems.

TL;DR: The proposed approach extends the S2QED approach to cover both single and multiple instruction bugs and ensures that a design is completely verified according to a well-defined criterion, which makes the approach robust against human errors.