This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Carbon nanotube devices offer intrinsic advantages for high-performance logic device applications. The ultrasmall body of a carbon nanotube-the tube diameter-is the key feature that should allow aggressive channel length scaling, while the intrinsic transport properties of the nanotube ensure at the same time high on-currents. In addition, the narrowness of the tube is critical to implementation of novel device concepts like the tunneling transistor. By understanding the unique capabilities of carbon nanotubes and using them in unconventional designs, novel nanoelectronic applications may become feasible. However, much better control of materials quality must be obtained, and new fabrication processes must be developed before such applications can be realized.

/pdf/carbon-nanotubes-for-high-performance-electronics-progress-1bj21dxqtf.pdf

Carbon Nanotubes for High-Performance Electronics—Progress and Prospect

This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs.

/pdf/toward-nanowire-electronics-2ea30585ug.pdf

Toward Nanowire Electronics

This paper presents a radio-frequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a 3-D device simulator. JLSNW MOSFETs are evaluated for various RF parameters such as cutoff frequency fT, gate input capacitance, distributed channel resistances, transport time delay, and capacitance by the drain-induced barrier lowering effect. Direct comparisons of high-frequency performances and extracted parameters are made with conventional silicon nanowire MOSFETs. A non-quasi-static RF model has been used, along with SPICE to simulate JLSNW MOSFETs with RF parameters extracted from 3-D-simulated Y-parameters. The results show excellent agreements with the 3-D-simulated results up to the high frequency of fT.

RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

GAA TSNWFET with 15 nm gate length and 4 nm radius nanowires is demonstrated and shows excellent short channel immunity. p-TSNWFET shows high driving current of 1.94 mA/?m while n-TSNWFET shows on-current on-current on-current of 1.44 mA/?m. Merits of TSNWFET and performance enhancement of p-TSNWFET are explored using 3-D and quantum simulation.

Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

As the DRAM design rule has been smaller, the leaning normally occurred in storage pattern with high aspect ratio also appears in STI (shallow trench isolation) pattern of sub 4Xnm device. IPA (isopropyl alcohol) showing the excellent ability to replace DIW (de-ionized water) is necessary in order to meet the leaning free condition, because the spin drying method cannot satisfy with leaning free condition.

Improved Drying Technology of Single Wafer Tool by Using Hot IPA/DIW

Introduction Silicon has been used successfully for semiconductor material because it can have a high degree of purity at a low cost, and shows the good mechanical, chemical and electrical properties. In the respect of electrical properties, the pure silicon is an insulator, thus the ion implantation process is necessary to make insulating silicon into semiconductor. Generally, the electrical properties of silicon based semiconductors are determined by the characteristics of dopant. Hence the study for the change of dopants concentration in following process such as ashing, strip, and annealing, is very important. (Shown in Figure 1.) In this study, we will discuss about the loss of dopant by strip process using fluorine-based stripper and annealing.

Effect of Ashing, Strip and Annealing Process on the Dopant Concentration of Silicon

Poly(methyl-co-cyclosiloxane bearing silsesquioxane)s (P(M-co-CSSQs)) were prepared. Using poly(e-caprolactone) (PCL) as a template, PCL / P(M-co-CSSQ) nanohybrid films were fabricated. The electrical, morphological, and mechanical properties of the PCL / P(M-co-CSSQ) films were investigated. The dielectric constant of a cured PCL / P(M-co-CSSQ) film at 420°C scaled down from 2.55 to 2.05 and refractive index from 1.41 to 1.33 when 20 vol. % of the PCL was admixed with the polymer matrix. The elastic modulus and hardness of the cured PCL / P(Mco- CSSQ) (2:8, vol./vol.) film were 2.50 and 0.32 GPa, respectively, showing dependency on the PCL content.

Characterization of nanoporous low dielectric polysilsesquioxane thin films

SiO2/poly-Si stack has been used successfully for complementary metal oxide semiconductor (CMOS) technology up to now because the silicon oxide and silicon have the good thermal, mechanical, chemical and electrical properties. However, as the dimension of semiconductor device becomes smaller, the metal gates and high-k materials are necessary to scale down CMOS device due to the increase of leakage current, power consumption, gate depletion and boron penetration in conventional SiO2/poly-Si stack. To replace n-poly and p-poly Si gate with metal electrodes, the dual metal gate system is required to meet the right work functions. As the respect of integration, a key factor in the dual metal gate process is the selective etch of the first metal gate without damage of the underlying high-k gate oxide and active before the deposition of the second metal [1,2,3]. Therefore the selective wet etch process is more efficient than the plasma etch which can damage to the high-k layer and active. A number of metals such as WN, TiN, TaSixNy and TaN have been researched for metal gate. Among them, TaN having the good thermal stability and controllable work function is evaluated as a good candidate for the electrode of dual metal gate. However, the development of the wet etch process of TaN has not been reported until recently. The previous report shows that the etch rate of TaN by SC1 solution is very low [2]. On the contrary, WN and TiN are well etched by SC1 based chemicals, which make easy the fabrication process employing WN or TiN as a metal gate. Since the behavior of tantalum is similar to that of a very noble metal, it is not attacked by any of the common acids and their mixtures [4]. This chemical resistance of TaN makes the wet etch process difficult in the dual metal gate system. In this reports, we will introduce a new TaN etchant showing high etch rate and damage-free to the gate high-k materials.

Mong Sup Lee

Papers

Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires

Improved Drying Technology of Single Wafer Tool by Using Hot IPA/DIW

Effect of Ashing, Strip and Annealing Process on the Dopant Concentration of Silicon

Characterization of nanoporous low dielectric polysilsesquioxane thin films

Development of a New TaN Etchant for Metal Gate