In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Phase Change Memory

Nonvolatile RAM using resistance contrast in phase-change materials [or phase-change RAM (PCRAM)] is a promising technology for future storage-class memory. However, such a technology can succeed only if it can scale smaller in size, given the increasingly tiny memory cells that are projected for future technology nodes (i.e., generations). We first discuss the critical aspects that may affect the scaling of PCRAM, including materials properties, power consumption during programming and read operations, thermal cross-talk between memory cells, and failure mechanisms. We then discuss experiments that directly address the scaling properties of the phase-change materials themselves, including studies of phase transitions in both nanoparticles and ultrathin films as a function of particle size and film thickness. This work in materials directly motivated the successful creation of a series of prototype PCRAM devices, which have been fabricated and tested at phase-change material cross-sections with extremely small dimensions as low as 3 nm × 20 nm. These device measurements provide a clear demonstration of the excellent scaling potential offered by this technology, and they are also consistent with the scaling behavior predicted by extensive device simulations. Finally, we discuss issues of device integration and cell design, manufacturability, and reliability.

Phase-change random access memory: a scalable technology

Mechanosensation electronics (or Electronic skin, e-skin) consists of mechanically flexible and stretchable sensor networks that can detect and quantify various stimuli to mimic the human somatosensory system, with the sensations of touch, heat/cold, and pain in skin through various sensory receptors and neural pathways. Here we present a skin-inspired highly stretchable and conformable matrix network (SCMN) that successfully expands the e-skin sensing functionality including but not limited to temperature, in-plane strain, humidity, light, magnetic field, pressure, and proximity. The actualized specific expandable sensor units integrated on a structured polyimide network, potentially in three-dimensional (3D) integration scheme, can also fulfill simultaneous multi-stimulus sensing and achieve an adjustable sensing range and large-area expandability. We further construct a personalized intelligent prosthesis and demonstrate its use in real-time spatial pressure mapping and temperature estimation. Looking forward, this SCMN has broader applications in humanoid robotics, new prosthetics, human-machine interfaces, and health-monitoring technologies.

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Skin-inspired highly stretchable and conformable matrix networks for multifunctional sensing

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology This has limited its usage to only the low levels of a memory hierarchy, eg, disks, that is far from the CPUIn this paper, we study the use of a new type of nonvolatile memories -- the Phase Change Memory (PCM) as the main memory for a 3D stacked chip The main challenges we face are the limited PCM endurance, longer access latencies, and higher dynamic power compared to the conventional DRAM technology We propose techniques to extend the endurance of the PCM to an average of 13 (for MLC PCM cell) to 22 (for SLC PCM) years We also study the design choices of implementing PCM to achieve the best tradeoff between energy and performance Our design reduced the total energy of an already low-power DRAM main memory of the same capacity by 65%, and energy-delay2 product by 60% These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency

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A durable and energy efficient main memory using phase change memory technology

A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Phase-change memory

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

A novel 3-D NAND flash memory device, VSAT (Vertical-Stacked-Array-Transistor), has successfully been achieved. The VSAT was realized through a cost-effective and straightforward process called PIPE (planarized-Integration-on-the-same-plane). The VSAT combined with PIPE forms a unique 3-D vertical integration method that may be exploited for ultra-high-density Flash memory chip and solid-state-drive (SSD) applications. The off-current level in the polysilicon-channel transistor dramatically decreases by five orders of magnitude by using an ultra-thin body of 20 nm thick and a double-gate-in-series structure. In addition, hydrogen annealing improves the subthreshold swing and the mobility of the polysilicon-channel transistor.

Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)

In this paper, the Phase Change Random Access Memory (PRAM, also known as Ovonic Unified Memory-OUM) cell, which has an extremely small and reproducible contact area and improved thermal environment, was fabricated and electrically characterized. The memory cell successfully operates with 30 ns pulses of 0.20 mA for RESET (high resistive) state and 0.13 mA for SET (low resistive) state. This is the best record of the published data.

An edge contact type cell for Phase Change RAM featuring very low power consumption

Nano scale body-tied FinFETs have been firstly fabricated. They have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 60 nm. This Omega MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I/sub SUB//I/sub D/ than planar type DRAM cell transistors.

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

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Joo Tae Moon

Papers

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)

An edge contact type cell for Phase Change RAM featuring very low power consumption

Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers

A stacked memory device on logic 3D technology for ultra-high-density data storage