Power grid verification has become an indispensable step to guarantee a functional and robust chip design. Vectorless power grid verification methods, by solving linear programming (LP) problems under current constraints, enable worst-case voltage drop predictions at an early stage of design when the specific waveforms of current drains are unknown. In this paper, a novel power grid verification algorithm based on hierarchical constraints is proposed. By introducing novel power constraints, the proposed algorithm generates more realistic current patterns and provides less pessimistic voltage drop predictions. The model order reduction-based coefficient computation algorithm reduces the complexity of formulating the LP problems from being proportional to steps to being independent of steps. Utilizing the special hierarchical constraint structure, the submodular polyhedron greedy algorithm dramatically reduces the complexity of solving the LP problems from over O(km3) to roughly O(kmlogkm), where km is the number of variables. Numerical results have shown that the proposed algorithm provides less pessimistic voltage drop prediction while at the same time achieves dramatic speedup.

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A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints

Vectorless power grid verification is a powerful method that evaluates worst-case voltage noises without detailed current waveforms using optimization techniques. It is extremely challenging when considering RLC power grids since inductors are difficult to tackle and multiple time steps should be evaluated after the discretization of the system equation. In this paper, we study integrated RLC power grids with both VDD and GND networks and rigorously prove that their vectorless verification can be decomposed into two sub-problems -- the well-studied transient power grid analysis problem and an optimization problem that maximizes an affine function of currents under current constraints. We further introduce transient constraints to restrict the waveform of each current source for realistic scenarios and design the RLCVN algorithm to solve the vectorless verification problem of RLC power grids. Results confirm that our algorithm is an effective approach for practical RLC power grid verification, and the proposed transient constraints make the noise estimations more realistic.

/pdf/vectorless-verification-of-rlc-power-grids-with-transient-1iesklfoxg.pdf

Vectorless verification of RLC power grids with transient current constraints

Vectorless power grid verification is a powerful method that evaluates worst-case voltage noises without detailed current waveforms using optimization techniques. It is extremely challenging when considering RLC power grids because inductors are difficult to tackle and multiple time steps should be evaluated after the discretization of the system equation. In this paper, we study integrated RLC power grids with both VDD and GND networks, and introduce transient constraints to restrict the waveform of each current source for sign-off verification. We rigorously prove that the vectorless verification can be decomposed into two subproblems-the well-studied power grid transient analysis problem and a linear programming (LP) problem that optimizes an affine function of currents under current constraints-and propose to verify the power grid by transient simulation and noise optimization. A variable reduction algorithm is further proposed to generate reduced-size LP problems with a user-specified error tolerance, so that the conservative bounds of voltage noises can be computed efficiently. Experimental results show that the proposed algorithm achieves significant speedup (e.g., up to more than 100t with 5 mV error) over the standard LP solver in solving the LP problems, and the proposed transient constraints make the noise estimations more realistic.

/pdf/verifying-rlc-power-grids-with-transient-current-constraints-2bilt664oh.pdf

Verifying RLC Power Grids With Transient Current Constraints

/pdf/vectorless-verification-of-rlc-power-grids-with-transient-uqv9ho48jk.pdf

Moondanos

Papers

Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis