Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement unsigned binary multiplier for mantissa multiplication. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

Floating point numbers are the quantities that cannot be represented by integers, either because they contain fractional values or because they lie outside the range re presentable within the system's bit width. Multiplication of two floating point numbers is very important for processors. Architecture for a fast floating point multiplier yielding with the single precision IEEE 754-2008 standard has been used in this project. The floating point representation can preserve the resolution and accuracy compared to fixed point. Pipeline is a technique where multiple instructions are overlapped in execution. Multiple operations performed at the same time by pipeline will increase the instruction throughput. In several high performance computing systems such as digital signal processors, FIR filters, microprocessors, etc multipliers are key components. The most important aim of the design is to make the multiplier quicker by decreasing delay. Decrease of delay can be caused by propagation of carry in the adders having smallest amount power delay constant.

Design and implementation of fast floating point multiplier unit

Arithmetic Logic Units (ALUs) are very important components of the processor, which performs various arithmetic and logical operations such as multiplication, division, addition, subtraction, cubing, squaring, etc. Of these all operations, multiplication is most elementary and most frequently used operation in the ALUs. The operation of multiplication also forms the basis of many other complex arithmetic operations such as cubing, squaring, convolution, etc. This paper presents the modified novel multi-precision binary multiplier architecture to achieve a reduced latency/delay and area/hardware utilization along with existing implementations of binary multiplication. This system will function as second stage of the of a novel multi-precision binary multiplier system. The system was implemented using Xilinx 14.2 ISE and simulated with ISIM which was available from Xilinx 14.2 ISE. The results of simulation indicate that the latency of the proposed novel binary multiplier systems (8-bit, 16-bit and 24-bit) with significantly shorter than existing implementations.

Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization

Binary multiplication is an important operation in many high power computing applications and floating point multiplier designs. And also multiplication is the most time, area and power consuming operation. This paper proposes an efficient method for unsigned binary multiplication which gives a better implementation in terms of delay and area. A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm (Vedic Mathematics) is used to implement the proposed unsigned binary multiplier. Karatsuba algorithm is best suited for higher bits and Urdhva-Tiryagbhyam algorithm is best for lower bit multiplication. A new algorithm by combining both helps to reduce the drawbacks of both. The multiplier is implemented using Verilog HDL, targeted on Spartan-3E and Virtex-4 FPGA.

An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm

This paper presents a fast single precision floating point multiplier In most of the industrial areas like DSP, image processing, microprocessor, it is needed to do arithmetic operations very fast with greater accuracy and multiplier is widely used in these application areas So we decide to increase the speed of floating point multiplication unit To improve the speed of multiplier we minimize the delays in arithmetic operations at every stage This is done by using Dadda algorithm for mantissa multiplication and Kogge-Stone adder for addition These two algorithms need more number of LUT-flip flop pairs but speed is increases The shifting technique is used to form partial product matrix which is new concept in Dadda algorithm, results in the optimization of design area All basic modules of this multiplier are written in Verilog hardware descriptive language and targeted to two families of FPGA, Virtex6 and Virtex5 in Xilinx 131 ISE software Design is simulated by using Model Sim63f Synthesis results of both FPGA are compares with previously designed multiplier unit Our design achieves maximum frequency of 851 MHz with 433 slices area and 1230 LUT-flip flop pairs in Virtex6 family

Design and verification of Dadda algorithm based Binary Floating Point Multiplier

An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant. The implementation of the multiplier module has been done in a top down approach. The sub-modules have been written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E FPGA.

Muchharla Suresh

Papers

FPGA design of a fast 32-bit floating point multiplier unit