Proceedings ArticleDOI
FPGA design of a fast 32-bit floating point multiplier unit
Anna Jain,Baisakhy Dash,Ajit Kumar Panda,Muchharla Suresh +3 more
- pp 545-547
TLDR
An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper and intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant.Abstract:
An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant. The implementation of the multiplier module has been done in a top down approach. The sub-modules have been written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E FPGA.read more
Citations
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Proceedings ArticleDOI
An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
S Arish,Rajender Kumar Sharma +1 more
TL;DR: A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm is used to implement unsigned binary multiplier for mantissa multiplication which gives a better implementation in terms of delay and power.
Proceedings ArticleDOI
Design and implementation of fast floating point multiplier unit
Sunesh N.V,Sathishkumar P +1 more
TL;DR: Architecture for a fast floating point multiplier yielding with the single precision IEEE 754-2008 standard has been used in this project to make the multiplier quicker by decreasing delay.
Journal ArticleDOI
Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization
TL;DR: The results of simulation indicate that the latency of the proposed novel binary multiplier systems (8-bit, 16-bit and 24-bit) with significantly shorter than existing implementations.
Proceedings ArticleDOI
An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
S Arish,Rajender Kumar Sharma +1 more
TL;DR: A combination of Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm is used to implement the proposed unsigned binary multiplier, which gives a better implementation in terms of delay and area.
Proceedings ArticleDOI
Design and verification of Dadda algorithm based Binary Floating Point Multiplier
TL;DR: A fast single precision floating point multiplier that achieves maximum frequency of 851 MHz with 433 slices area and 1230 LUT-flip flop pairs in Virtex6 family is presented.
References
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Book
Computer Organization
TL;DR: The book highlights modern developments in computer design,I/O and performance and presents real system examples from around the world.
Proceedings ArticleDOI
Double precision floating-point arithmetic on FPGAs
Stavros Paschalakis,Peter Lee +1 more
TL;DR: This work presents low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addition/subtraction, multiplication, division and square root, and considers the implementation of 64-bit double precision circuits that also provide rounding and exception handling.
Proceedings ArticleDOI
Design of Generic Floating Point Multiplier and Adder/Subtractor Units
TL;DR: A novel multiplication algorithm is proposed and used in the multiplier implementation and depends on dividing the multiplication operation into several smaller multiplications performed in parallel to give the final result of the original multiplication operation.
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