M
Myoung-Bum Lee
Researcher at Samsung
Publications - 60
Citations - 1337
Myoung-Bum Lee is an academic researcher from Samsung. The author has contributed to research in topics: Layer (electronics) & Gate oxide. The author has an hindex of 17, co-authored 60 publications receiving 1332 citations.
Papers
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Patent
Nonvolatile memory device and method for fabricating the same
Soo-doo Chae,Myoung-Bum Lee,Hui-chang Moon,Han-soo Kim,Jin-Gyun Kim,Ki-Hyun Kim,Si-Young Choi,Hoosung Cho +7 more
TL;DR: In this article, a three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars and gate electrodes.
Patent
Vertical memory devices and methods of manufacturing the same
TL;DR: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, channels arranged in vertical openings formed through at least some of the layers, and a remaining area of the portion not occupied by the conductive barrier or filling layer pattern as mentioned in this paper.
Patent
Semiconductor memory device and method of fabricating the same
TL;DR: In this paper, the first and second gate conductive layers of a semiconductor memory device are stacked on top of each other, and the second gate conductsance is extended to continuously cover surfaces of the first gate conductance.
Patent
Semiconductor memory devices and methods of forming the same
Jung Ho Kim,Daehyun Jang,Myoung-Bum Lee,Ki-Hyun Hwang,Sang-Ryol Yang,Yong-Hoon Son,J. M. Kim,Sung-Hae Lee,Dongwoo Kim,Jin-Gyun Kim +9 more
TL;DR: In this article, a method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate, and then removing a portion of the buried layer to create a second through region between the sidewalls of the first layer and the second layer.
Patent
Semiconductor memory device having insulation patterns and cell gate patterns
TL;DR: In this article, the authors present a method of forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layer and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gates in the opening.