Han-soo Kim

TL;DR: Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.

TL;DR: In this article, a three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars and gate electrodes.

TL;DR: The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1 × nm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution.

TL;DR: A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality-of- elongated word lines, each word line including a first portion substantially parallel to substrate and connected to memory string and a second portion substantially inclined relative to substrate, and extending above the substrate as discussed by the authors.

TL;DR: In this paper, the first selection line is connected to the at least one pair of first selection transistors of the NAND string and a plurality of word lines are coupled to the plurality of memory cells.