Teramac is a massively parallel experimental computer built at Hewlett-Packard Laboratories to investigate a wide range of different computational architectures. This machine contains about 220,000 hardware defects, any one of which could prove fatal to a conventional computer, and yet it operated 100 times faster than a high-end single-processor workstation for some of its configurations. The defect-tolerant architecture of Teramac, which incorporates a high communication bandwith that enables it to easily route around defects, has significant implications for any future nanometer-scale computational paradigm. It may be feasible to chemically synthesize individual electronic components with less than a 100 percent yield, assemble them into systems with appreciable uncertainty in their connectivity, and still create a powerful and reliable data communications network. Future nanoscale computers may consist of extremely large-configuration memories that are programmed for specific tasks by a tutor that locates and tags the defects in the system.

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A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology

Reprogrammable systems based on field programmable gate arrays are revolutionizing some forms of computation and digital logic. As a logic emulation system, they provide orders of magnitude faster computation than software simulation. As a custom-computing machine, they achieve the highest performance implementation for many types of applications. As a multimode system, they yield significant hardware savings and provide truly generic hardware. In this paper, we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems.

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The roles of FPGAs in reprogrammable systems

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit "defect tolerant", i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

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Defect tolerance in VLSI circuits: techniques and yield analysis

Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's) The physical design is partitioned into a set of tiles In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead

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Low overhead fault-tolerant FPGA systems

Teramac is a large custom computer which works correctly despite the fact that three quarters of its FPGAs contain defects. This is accomplished through unprecedented use of defect tolerance, which substantially reduces Teramac's cost and permits it to have an unusually complex interconnection network. Teramac tolerates defective resources, like gates and wires, that are introduced during the manufacture of its FPGAs and other components, and during assembly of the system. We have developed methods to precisely locate defects. User designs are mapped onto the system by a completely automated process that avoids the defects and hides the defect tolerance from the user. Defective components are not physically removed from the system.

Defect tolerance on the Teramac custom computer

The fine granularity and reconfigurable nature of field-programmable gate arrays (FPGA's) suggest that defect-tolerant methods can be readily applied to these devices in order to increase their maximum economic sizes, through increased yield. This paper identifies the inability to contain faults within single cells and the need for fast reconfiguration as the key obstacles to obtaining a significant increase in yield. Monte Carlo defect modeling of the photolithographic layers of VLSI FPGA's is used as a foundation for the yield modeling of various defect-tolerant architectures. Results suggest that a medium-grain architecture is the best solution, offering a substantial increase in size without significant side effects. This architecture is shown to produce greater gate densities than the alternative approach of realizing ultralarge scale FPGA's-multichip modules. >

The yield enhancement of field-programmable gate arrays

The York fuzzy automata machine (FAMe) is a massively parallel fuzzy cellular automata machine, capable of a wide range of computation. Rather than a fixed architecture, FAMe makes use of reconfigurable logic for implementing the most appropriate hardware for a given program. The authors describe the structure of the fuzzy automata machine and show how large complex fuzzy parallel systems may be constructed. A simple example of the use of FAMe involving fuzzy logic is given. >

The design and implementation of a massively-parallel fuzzy architecture

FPGA acceleration of electronic design automation tasks

This paper investigates the possibility of using Field-Programmable Gate Arrays (Fr’GAS) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of FPGAS as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various FPGA co-processor arrangements.

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The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

Zelig is a 32 physical node fine-grained computer employing field-programmable gate arrays Its application to the high speed implementation of various image pre-processing operations (in particular binary morphology) is described together with typical speed-up results

N.J. Howard

Papers

The yield enhancement of field-programmable gate arrays

The design and implementation of a massively-parallel fuzzy architecture

FPGA acceleration of electronic design automation tasks

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

Image processing applications using a novel parallel computing machine based on reconfigurable logic