This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the state-of-the-art after two decades of research in recursive bisection placement and implement a new placer, called Capo, to empirically study the achievable limits of the approach. From among recently proposed improvements to recursive bisection, Capo incorporates a leading-edge multilevel min-cut partitioner [7], techniques for partitioning with small tolerance [8], optimal min-cut partitioners and end-case min-wirelength placers [5], previously unpublished partitioning tolerance computations, and block splitting heuristics. On the other hand, our “good enough” implementation does not use “overlapping” [17], multi-way partitioners [17, 20], analytical placement, or congestion estimation [24, 35]. In order to run on recent industrial placement instances, Capo must take into account fixed macros, power stripes and rows with different allowed cell orientations. Capo reads industry-standard LEF/DEF, as well as formats of the GSRC bookshelf for VLSI CAD algorithms [6], to enable comparisons on available placement instances in the fixed-die regime.Capo clearly demonstrates that despite a potential mismatch of objectives, improved mincut bisection can still lead to improved placement wirelength and congestion. Our experiments on recent industrial benchmarks fail to give a clear answer to the question in the title of this paper. However, they validate a series of improvements to recursive bisection and point out a need for transparent congestion management techniques that do not worsen the wirelength of already routable placements. Our experimental flow, which validates fixed-die placement results by violation-free detailed auto-routability, provides a new norm for comparison of VLSI placement implementations.

Can recursive bisection alone produce routable placements

A system and method for timing-closed placement which also takes wirelength and congestion into consideration. In one aspect, the system and method of timing driven placement according to the present invention incorporates a timing budget management technique which satisfies triangle parity and inequality, a timing-driven quadrisection placement strategy based on flexible timing window configurations to minimize the wirelength and congestion during each mincut quad-partition of top-down hierarchy, and a linear programming formulation incorporating bin capacity, channel capacity and congestion criticality.

Timing-driven global placement based on geometry-aware timing budgets

Partitioning plays an increasingly important role in the design process of VLSI circuits and systems. There are partitioning problems to be solved on all levels of abstraction. The rapidly increasing size of the designs will make good partitioning tools even more essential in the future. As an introduction to the other papers in this session, this tutorial presentation discusses the numerous facets of partitioning.

/pdf/partitioning-of-vlsi-circuits-and-systems-2bepytnsdn.pdf

Partitioning of VLSI circuits and systems

A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is used to optimize cell placement by swapping cells between two or more rows. The search space is pruned beforehand. A greedy cleanup phase using an incremental row placer is used. Thereby, the detailed placement process handles congestion driven placements characterized by non-uniform densities expeditiously and efficiently.

Detailed placer for optimizing high density cell placement in a linear runtime

Very large scale integration (VLSI) fabrication technology has advanced rapidly, bringing with it a strong demand for faster and better design automation tools. Accurate reporting of results for placement approaches is crucial to the development of improved automation tools; unfortunately, publicly available placement benchmarks are outdated, and there are wide variations in their interpretation. In addition, the metrics considered by some academic research have questionable relevance to modern design. At best, poor benchmarks and differences in interpretation result in misunderstandings of the effectiveness of some approaches. At worst, they can motivate research in areas of very little promise, while other areas which have true potential are ignored. In this paper, we expand on work previously presented, describing current standard cell placement benchmarks and illustrating common differences in their interpretation. We also propose specific interpretation methods for traditional objectives, and discuss new metrics which should be considered in modern placement research. Our hope is that by presenting these issues clearly, we can enable more accurate evaluations of placement methods, and improve research efficiency.

/pdf/reporting-of-standard-cell-placement-results-1r2mqgak6w.pdf

Reporting of standard cell placement results

In this paper, we present a new performance driven placement method based on path delay constraint approach for large standard cell layout. The proposed method consists of three phases and uses the Elmore delay model to model interconnection delay precisely in each phase. In the first phase, initial placement is performed by an efficient performance driven mincut partitioning method. Next, an iterative improvement method by nonlinear programming improves the layout. The improvement is formulated as the problem of minimizing the total wire length subject to critical path delays. Finally, row assignment considering timing constraint is performed. From the experimental results, the proposed method is much better than RITUAL in point of the maximal violation ratio, the total wire length, and the cut size, and is more effective in the interconnection delay model and its extendability.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1995/aspdac95/pdffiles/8a_2.pdf

A new performance driven placement method with the Elmore delay model for row based VLSIs

In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1995/aspdac95/pdffiles/3a_1.pdf

A new system partitioning method under performance and physical constraints for multi-chip modules

We present a new cell model for over-the-cell routing and a new over-the cell multi-channel routing method. In the proposed new cell model, terminals can be placed arbitrarily on the second layer of a cell so that each cell does not require the extra routing region on the first layer of a cell to align terminals. Unlike conventional cell models, some parts of the second layer are also utilized for the intra-cell routing in order to reduce the chip area. Therefore the size of the proposed cell model can be smaller than that of a conventional cell model. The proposed method consists of three phases. In order to utilize the proposed cell model, in phase 1, we simultaneously handle all channels to determine the most effective routing patterns from the set of possible routing patterns to minimize the chip area. In phase 2, for the effective routing patterns of nets selected in phase 1, over-the-cell routing nets are selected by a new greedy algorithm considering obstacles on over-the-cells. Finally, the conventional channel routing algorithm is applied for nets unrouted on over-the-cell. From the experimental results with MCNC benchmarks, the proposed cell model and algorithm produce smaller height of layouts as compared to those produced by conventional cell models and algorithms, and the effectiveness of the proposed method and cell model was shown.

/pdf/a-three-layer-over-the-cell-multi-channel-routing-method-for-29pdmqe7o2.pdf

A three-layer over-the-cell multi-channel routing method for a new cell model

http://ieeexplore.ieee.org/iel2/3478/10306/00486223.pdf

N. Yoshida

Papers

A new performance driven placement method with the Elmore delay model for row based VLSIs

A new performance driven placement method with the Elmore delay model for row based VLSIs

A new system partitioning method under performance and physical constraints for multi-chip modules

A three-layer over-the-cell multi-channel routing method for a new cell model

A three-layer over-the-cell multi-channel routing method for a new cell model