This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

The Artificial Intelligence field continues to be plagued by what can only be described as ‘bold promises for the future syndrome’, often perpetrated by researchers who should know better. While impartial assessment can point to concrete contributions over the past 50 years (such as automated theorem proving, games strategies, the LISP and Prolog high-level computer languages, Automatic Speech Recognition, Natural Language Processing, mobile robot path planning, unmanned vehicles, humanoid robots, data mining, and more), the more cynical argue that AI has witnessed more than its fair share of ‘unmitigated disasters’ during this time – see, for example [3,58,107,125,186]. The general public becomes rapidly jaded with such ‘bold predictions’ that fail to live up to their original hype, and which ultimately render the zealots’ promises as counter-productive.

Computational Intelligence: An Introduction

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

https://www.cse.iitk.ac.in/users/isaha/Publications/Journals/NC10.pdf/

Artificial neural networks in hardware: A survey of two decades of progress

Cours d'economie politique

The aim of the work described in this article is to investigate migration strategies for the execution of parallel genetic algorithms in a multi-processor system-on-chip (MPSoC) Some multimedia and internet applications for wireless communications are using genetic algorithms and can benefit from the advantages provided by parallel processing on MPSoCs In order to run such algorithms, we use a network-on-chip platform, which provides the interconnection network required for the communication between processors Two migration strategies are employed in order to analyse the speedup and efficiency each one can provide, considering the communication costs they require

Migration selection of strategies for parallel genetic algorithms: implementation on networks on chips

In this paper, we propose reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. This is used to build a feed-forward artificial neural network. For this purpose, we use field- programmable gate arrays i.e. FPGAs. However, as the state-of-the-art FPGAsstill lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement the computation performed by a neuron. The multiplication an addition of stochastic values is simply implemented by an ensemble of XNORand ANDgates respectively.

Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron

This paper is focused on the hardware implementation of neural networks. It describes the characteristics of two architectures designed to implement feed-forward fully connected artificial neural networks: the first FPGA prototype is based on traditional adders and multipliers of binary inputs, while the second takes advantage of stochastic representation of the inputs. The paper compares both prototypes using the time/spl times/area classic factor.

FPGA-based hardware architecture for neural networks: binary radix vs. stochastic

The particle swarm optimisation or PSO is a heuristic based on a population of individuals, in which the candidates for a solution of the problem at hand evolve through a simulation process of a social adaptation simplified model. Combining robustness, efficiency and simplicity, PSO has gained great popularity as many successful applications are reported. The algorithm has proven to have several advantages over other algorithms that are based on swarm intelligence principles. The use of PSO for solving problems that involve computationally demanding functions often results in low performance. In order to accelerate the process, one can proceed with the parallelisation of the algorithm and/or mapping it directly onto hardware. This paper presents a novel massively parallel co-processor for PSO implemented in reconfigurable hardware. The implementation results show that the proposed architecture is very promising as it achieved superior performance in terms of execution time when compared to the direct software execution of the algorithm.

Parallel co-processor for PSO

In a scenario wherein several tasks must be done cooperatively by a robotic swarm, it is sometimes mandatory to prescribe the robots that should execute each one of those tasks. A problem related to the division of labour among the swarm members is the robot recruitment. When a specific robot needs assistance, it must create a group, selecting other robots to help in the execution of the given task. The main contribution of this work is the development of a distributed recruitment strategy based mainly on the propagation of messages among neighbouring robots. The algorithm is evaluated through simulations, wherein some recruitment features are analysed by subjecting the swarm to different conditions, such as the total number of robots in the swarm and the number of robots that start the recruitment. This strategy is promising, since robots have no global knowledge about the swarm, relying only in the neighbourhood information.

Nadia Nedjah

Papers

Migration selection of strategies for parallel genetic algorithms: implementation on networks on chips

Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron

FPGA-based hardware architecture for neural networks: binary radix vs. stochastic

Parallel co-processor for PSO

Distributed strategy for robots recruitment in swarm-based systems