International Journal of High Performance Systems Architecture 

About: International Journal of High Performance Systems Architecture is an academic journal published by Inderscience Publishers. The journal publishes majorly in the area(s): Computer science & Network on a chip. It has an ISSN identifier of 1751-6528. Over the lifetime, 176 publications have been published receiving 919 citations. The journal is also known as: High performance systems architecture & IJHPSA.

A survey of architectural techniques for DRAM power management

Abstract: Recent trends of CMOS technology scaling and wide-spread use of multicore processors have dramatically increased the power consumption of main memory. It has been estimated that modern data-centres spend more than 30% of their total power consumption in main memory alone. This excessive power dissipation has created the problem of 'memory power wall' which has emerged as a major design constraint inhibiting further performance scaling. Recently, several techniques have been proposed to address this issue. The focus of this paper is to survey several architectural techniques designed for improving power efficiency of main memory systems, specifically DRAM systems. To help the reader in gaining insights into the similarities and differences between the techniques, this paper also presents a classification of the techniques on the basis of their characteristics. The aim of this paper is to equip the engineers and architects with knowledge of the state of the art DRAM power saving techniques and motivate them to design novel solutions for addressing the challenges presented by the memory power wall problem.

Genetic programming on GPUs for image processing

Abstract: The evolution of image filters using genetic programming is a relatively unexplored task. This is most likely due to the high computational cost of evaluating the evolved programs. The parallel processors available on modern graphics cards can be used to greatly increase the speed of evaluation. Previous papers in this area dealt with tasks such as noise reduction and edge detection. Here we demonstrate that other more complicated processes can also be successfully evolved and that we can 'reverse engineer' the output from filters used in common graphics manipulation programs.

Resilience to churn of a peer-to-peer evolutionary algorithm

Abstract: In this paper we analyse the resilience of a peer-to-peer (P2P) evolutionary algorithm (EA) subject to the following dynamics: computing nodes acting as peers leave the system independently from each other causing a collective effect known as churn. Since the P2P EA has been designed to tackle large instances of computationally expensive problems, we will assess its behaviour under these conditions, by performing a scalability analysis in five different scenarios using the massively multimodal deceptive problem as a benchmark. In all cases, the P2P EA reaches the success criterion without a penalty on the runtime. We show that the key to the algorithm resilience is to ensure enough peers at the beginning of the experiment; even if some of them leave, those that remain contain enough information to guarantee a reliable convergence.

Minimising the delta test for variable selection in regression problems

Abstract: The problem of selecting an adequate set of variables from a given data set of a sampled function becomes crucial by the time of designing the model that will approximate it. Several approaches have been presented in the literature although recent studies showed how the delta test is a powerful tool to determine if a subset of variables is correct. This paper presents new methodologies based on the delta test such as tabu search, genetic algorithms and the hybridisation of them, to determine a subset of variables which is representative of a function. The paper considers as well the scaling problem where a relevance value is assigned to each variable. The new algorithms were adapted to be run in parallel architectures so better performances could be obtained in a small amount of time, presenting great robustness and scalability.

Network-on-chip architecture design based on mesh-of-tree deterministic routing topology

Abstract: Network-on-Chip (NoC) is a new paradigm for designing future System-on-Chips (SoCs) where large numbers of Intellectual Property (IP) cores are connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present NoC architecture based on Mesh-of-Tree (MoT) deterministic routing. MoT interconnection has the advantage of having small diameter as well as large bisection width. It is known as the fastest network when considered solely in terms of speed. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free. We also present how Globally Asynchronous Locally Synchronous (GALS) style of communication has been implemented by using FIFO in mixed clock system.