3D IC is a promising technology to meet the demands of high throughput, high scalability, and low power consumption for future generation integrated circuits. One way to implement the 3D IC is to interconnect layers of two-dimensional (2D) IC with Through-Silicon Via (TSV), which shortens the signal lengths. Unfortunately, while TSVs are bundled together as a cluster, the crosstalk coupling noise may lead to transmission errors. As a result, the working frequency of TSVs has to be lowered to avoid the errors, leading to narrower bandwidth that TSVs can provide. In this paper, we first derive the crosstalk noise model from the perspective of 3D chip and then propose ShieldUS, a runtime data-to-TSVs remapping strategy. With ShieldUS, the transition patterns of data over TSVs are observed at runtime, and relatively stable bits will be mapped to the TSVs which act as shields to protect the other bits which have more fluctuations. We evaluate the performance of ShieldUS with address lines from real benchmark traces and data lines of different similarities. The results show that ShieldUS is accurate and flexible. We further study dynamic shielding and our design of Interval Equilibration Unit (IEU) can intelligently select suitable parameters for dynamic shielding, which makes dynamic shielding practical and does not need to predefine parameters. This also improves the practicability of ShieldUS.

/pdf/shieldus-a-novel-design-of-dynamic-shielding-for-eliminating-2llj7snxo9.pdf

ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise

The energy consumption of a graphics processing unit (GPU) is an important factor in its design, whether for a server, desktop, or mobile device. Mobile products, such as smart phones, tablets, and laptop computers, rely on batteries to function; the less the demand for power is on these batteries, the longer they will last before needing to be recharged. GPUs used in servers and desktops, while not dependent on a battery for operation, are still limited by the efficiency of power supplies and heat dissipation techniques. In this dissertation, I propose to lower the energy consumption of GPUs by reducing the precision of floating-point arithmetic in the graphics pipeline and the data sent and stored on- and off-chip. 
The key idea behind this work is twofold: energy can be saved through a systematic and targeted reduction in the number of bits 1) computed and 2) communicated. Reducing the number of bits computed will necessarily reduce either the precision or range of a floating point number. I focus on saving energy by way of reducing precision, which can exploit the over-provisioning of bits in many stages of the graphics pipeline. Reducing the number of bits communicated takes several forms. First, I propose enhancements to existing compression schemes for off-chip buffers to save bandwidth. I also suggest a simple extension that exploits unused bits in reduced-precision data undergoing compression. Finally, I present techniques for saving energy in on-chip communication of reduced-precision data. 
By designing and simulating variable-precision arithmetic circuits with promising energy versus precision characteristics and tradeoffs, I have developed an energy model for GPUs. Using this model and my techniques, I have shown that significant savings (up to 70% in computation in the vertex and pixel shader stages) are possible by reducing the precision of the arithmetic. Further, my compression approaches have enabled improvements of 1.26x over past work, and a general-purpose compressor design has achieved bandwidth savings of 34%, 87%, and 65% for color, depth, and geometry data, respectively, which is competitive with past work. Lastly, an initial exploration in signal gating unused lines in on-chip buses has suggested savings of 13-48% for the tested applications' traffic from a multiprocessor's register file to its L1 cache.

https://cdr.lib.unc.edu/downloads/5999n485c

Energy-precision tradeoffs in the graphics pipeline

For System on-chip (SoC) designs in current Deep Submicron (DSM) era, interconnects play important role in overall performance of the chip. The factors such as propagation delay, power dissipation and crosstalk through RC modeled interconnects substantially affects the entire working of the chip. Functional crosstalk and crosstalk induced propagation delay have recently emerged as major sources of faults. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition in previous state of wire as well as when transitions are in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. This paper proposes encoding schemes in order to achieve reduction in transitions between the previous and present states of wire as well as transitions in adjacent wires. The reduction in transition improves the performance in terms of power dissipation, coupling activity and delay in on-chip bus.

Crosstalk and Power Reduction Using Bus Encoding in RC Coupled VLSI Interconnects

In this paper we propose two bus encoding algorithms that optimize both bus delay and energy dissipation based on the probabilistic characteristics of data on data buses. The first algorithm minimizes the crosstalk transitions by inserting temporal redundancy and achieves optimal energy. The second algorithm reduces crosstalk more aggressively to achieve optimal bus delay by mapping the original data to low-energy opposite-transition-forbidden codes. Experimental results show that they outperform the existing heuristic bus encoding algorithms by 15.7% to 58.8% in average energy dissipation and 11.4% to 58.4% in average delay.

Bus encoding for simultaneous delay and energy optimization

In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.

http://it-in-industry.org/index.php/itii/article/download/151/135

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

Delay-efficient bus encoding techniques

On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but the propagation delay is data dependent and data is application dependent. Different applications may have different data behavior. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give different performance results.In this paper, by exploiting data behavior, we propose two on-chip delay minimization techniques, namely, data packing and data permutation. We validate our techniques by focusing on the L1 cache address/data buses using SPEC2000 CINT benchmarks. We show that, in the address bus case, the data packing and data permutation techniques achieve more than 2.3X and 1.6X speedup, respectively, over the unencoded bus, whereas in the case of data bus, both these techniques achieve more than 1.5X and 1.4X speedup, respectively. For a 32-bit bus, both data packing and data permutation techniques require 38 and 34 wires, respectively.

Nallamothu Satyanarayana

Papers

Delay-efficient bus encoding techniques

Exploiting on-chip data behavior for delay minimization