There is provided a pellicle in which the mask-bonding agglutinant layer has the adhesion strength of 1 N/m through 100 N/m, preferably 4 N/m through 80 N/m, and more preferably the agglutinant layer has a facial flatness of 15 micrometers or smaller, and still more preferably the membrane-bonding adhesive layer has a facial flatness of 15 micrometers or smaller: for the purpose of better preventing the pellicle frame from affecting the mask to deform.

Pellicle for lithography

Routing congestion model is of great importance in design stages of modern physical synthesis, e.g. global routing and routability estimation during placement. As the technology node becomes smaller, routing congestion is more difficult to estimate during design stages ahead of detailed routing. In this paper, we propose a framework using nonparametric regression technique in machine learning to construct routing congestion model. The constructed model can capture multiple factors and enables direct prediction of detailed routing congestion with high accuracy. By using this model in global routing, significant reduction of design rule violations and detailed routing runtime can be achieved compared with the model in previous work, with small overhead in global routing runtime and memory usage.

Accurate prediction of detailed routing congestion using supervised data learning

Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult due to the complexity and uncertainty of routing. In this paper, we propose a new detailed routing routability prediction model based on supervised learning. After extracting key features in placement and detailed routing, multivariate adaptive regression is performed to train the connection between these two stages. Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage. Experiments show that our average prediction accuracy is 79.8%, which is comparable with other state-of-art routability estimation techniques.

An accurate detailed routing routability prediction model in placement

Machine learning (ML) and pattern matching (PM) are powerful computer science techniques which can derive knowledge from big data, and provide prediction and matching. Since nanometer VLSI design and manufacturing have extremely high complexity and gigantic data, there has been a surge recently in applying and adapting machine learning and pattern matching techniques in VLSI physical design (including physical verification), e.g., lithography hotspot detection and data/pattern-driven physical design, as ML and PM can raise the level of abstraction from detailed physics-based simulations and provide reasonably good quality-of-result. In this paper, we will discuss key techniques and recent results of machine learning and pattern matching, with their applications in physical design.

Machine learning and pattern matching in physical design

Placement is considered a fundamental physical design problem in electronic design automation. It has been around so long that it is commonly viewed as a solved problem. However, placement is not just another design automation problem; placement quality is at the heart of design quality in terms of timing closure, routability, area, power and most importantly, time-to-market. Small improvements in placement quality often translate into large improvements further down the design closure stack. This paper makes the case that placement is a "hot topic" in design automation and presents several placement formulations related to routability, clocking, datapath, timing, and constraint management to drive years of research.

Placement: hot or not?

Physical synthesis has emerged as one of the most important tools in design closure, which starts with the logic synthesis step and generates a new optimized netlist and its layout for the final signoff process. As stated in [1], "it is a wrapper around traditional place and route, whereby synthesis-based optimization are interwoven with placement and routing." A traditional physical synthesis tool generally focuses on design closure with Steiner wire model. It optimizes timing/area/power with the assumption that each net can be routed with optimal Steiner tree. However, advanced design rules, more IP and hierarchical design styles for super-large billion-gate designs, serious buffering problems from interconnect scaling and metal layer stacks make routing a much more challenging problem [2]. This paper discusses a series of techniques that may relieve this problem, and guide the physical design closure system to produce not only easier to route designs, but also better timing quality. Open challenges are also overviewed at the end.

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing

This work proposes a novel latch placement methodology by computing optimized placement templates with significantly lower local clock tree capacitance at a one-time cost per standard cell library. By directly minimizing local clock tree capacitance, overall chip power is reduced. The proposed methodology first generates optimized placement solutions for a wide range of input configurations. Then, a redundancy removal approach using set-theoretic annotation is proposed demonstrating it is possible to remove over 99% of the templates with no information loss. Finally, a decision tree induction algorithm with novel impurity metric enables extremely fast template selection during the clock optimization stage of a modern physical design flow. The proposed approach reduces the local clock tree capacitance by 20-30% on average roughly equating to between a 1 and 4 watt reduction in total dynamic power on a 100-watt 22-nm microprocessor. Additionally, because of a priori generation, template selection during physical design is extremely fast.

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Clock power minimization using structured latch templates and decision tree induction

Advanced immersion lithography utilizes higher numerical aperture (NA) stepper lenses resulting in higher angles of light illumination through photomasks. Transmission in conventional pellicles (830 nm thickness) is generally maximized at 0 degree illumination and decreases significantly at the higher angles. Most pellicle suppliers have developed thinner pellicle membranes (~280 nm) which allow considerably improved transmission of light at angles up to 20 degrees. In addition, aluminum frames have been shortened, potentially allowing inspection closer to the inside of the frame and reduced mask flatness distortion upon pellicle mount. Suppliers have also developed advanced adhesives which reduce outgassing even beyond the low levels obtained with current 45 nm pellicles. In this paper, advanced immersion pellicles from several suppliers are evaluated and compared with conventional 45 nm pellicles for the following quality parameters: physical durability, foreign material, ease of demounting and glue removal, chemical outgassing, mask flatness distortion and susceptibility to radiation damage. Improvements in mask inspection and pellicle optical transmission at higher incident angles are also evaluated and are discussed. Keywords : Mask flatness, pellicle, adhesive, frame

Evaluation of 32nm advanced immersion lithography pellicles

Clock grid is a mainstream clock network methodology for high performance microprocessor and SOC designs. Clock skew, power usage and robustness to PVT (power, voltage, temperature) are all important metrics for a high quality clock grid design. Tree-driven-grid clock network is a typical clock grid clock network. It includes a clock source, a buffered tree, leaf buffers, a mesh clock grid, local clock buffers, and latches as shown in Fig. 1. For such network, one big challenge is how to connect the leaf level buffers of the global tree to the grid with nonuniform loads under tight slew and skew constraints. The choice of tapping points that connect the leaf buffers to the clock grid are critical to the quality of the clock designs. Good tapping points can minimize the clock skew and reduce power. In this paper, we proposed a new algorithm to select the tapping points to build the global tree as regular and symmetric as possible. From our experimental results, the proposed algorithm can efficiently reduce global clock skew, rising slew, maximum overshoot, reduce power, and avoid local skew violation.

PACMAN: Driving Nonuniform Clock Grid Loads for low-skew robust clock network

Previous work has shown that photomask blank flatness as well as photomask patterning and pelliclization all play an
important role in finished photomask flatness. Additional studies have shown that pellicle mounting techniques,
pellicle adhesives, frame flatness and shape and pellicle mounting tools play a role as well. It has become clear that
frame flexibility, coupled with frame mounting surface flatness and shape are the principal factors influencing the
pellicle effect on the mask distortion. Pellicle suppliers have begun to evaluate various polymers as potential
replacements for the standard aluminum frame in current use. The elasticity of the frame adhesive has also been adjusted
to evaluate its effect on the pellicle influence on mask flatness.
This paper describes some joint evaluations between IBM, Toppan and ShinEtsu, performed to determine the effect of
pellicle frame composition,, mount surface flatness, adhesive elasticity and adhesive surface flatness on the distortion of
photolithography masks. It demonstrates that polymer pellicle frames with more flexible adhesive improve finished
mask flatness approximately the same amount as reducing the total frame standoff height of aluminum frames with
conventional adhesive.

Nancy Zhou

Papers

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing

Clock power minimization using structured latch templates and decision tree induction

Evaluation of 32nm advanced immersion lithography pellicles

PACMAN: Driving Nonuniform Clock Grid Loads for low-skew robust clock network

Effect of pellicle frame and adhesive material on final photomask flatness