This paper presents a class of count-and-threshold mechanisms, collectively named /spl alpha/-count, which are able to discriminate between transient faults and intermittent faults in computing systems. For many years, commercial systems have been using transient fault discrimination via threshold-based techniques. We aim to contribute to the utility of count-and-threshold schemes, by exploring their effects on the system. We adopt a mathematically defined structure, which is simple enough to analyze by standard tools. /spl alpha/-count is equipped with internal parameters that can be tuned to suit environmental variables (such as transient fault rate, intermittent fault occurrence patterns). We carried out an extensive behavior analysis for two versions of the count-and-threshold scheme, assuming, first, exponentially distributed fault occurrencies and, then, more realistic fault patterns.

Threshold-based mechanisms to discriminate transient from intermittent faults

The present invention employs a high density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns. All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.

Integrated circuit packaging configuration for rapid customized design and unique test capability

The Power4 is an integrated system on a chip (SoC) designed for systems that will initially target enterprise Unix customers and, at a later date, O/S 400 customers. Power4 systems are servers comprised of several Power4 chips. To achieve reliability goals, Power4 system design incorporates fault tolerance throughout the hardware, firmware and operating system. Together, these system components provide concurrent and deferred maintenance, multi-level recovery from errors and run-time diagnostics.

Power4 system design for high reliability

The author surveys the approaches and techniques used to improve system reliability. Over the past 40 years computing systems have experienced over three orders of magnitude improvement in average time to failure and over six orders of magnitude improvement in work accomplished between outages. A three-dimensional design space for comparing fault-tolerant systems is proposed and populated by over two dozen actual systems. A detailed description is provided for a dozen systems evenly distributed throughout the design space. The author concludes by observing trends in the design space and projecting future developments. >

Architecture of fault-tolerant computers: an historical perspective

A programmable fault injection tool (PFIT) for the 
testing of the diagnostic capabilities of a computer or 
digital processing system (16) is disclosed. The PFIT is made 
up of event compare hardware (13) and error injection hardware 
(14). The event compare hardware of the PFIT is user pro­
grammable through menu-driven software to compare a particular 
stored event, either a digital word or sequence of words, with 
an event measured within the system under test. The stored 
event can be changed by the user under program control so as 
to provide a generalized fault injection tool (11). In 
addition, the tool includes a mask memory (58) that allows 
certain bits in an word to be masked, or ignored, when the 
state of the bit within the word is inconsequential. The error injection hardware (14) of the PFIT is con­
trolled by the event compare hardware (13) to inject faults by 
short circuiting voltage nodes within the system under test to 
ground or a supply voltage. The error injection hardware will 
inject the fault for a user specified time duration and only 
after a user specified time delay.

Programmable fault injection tool

The concepts of automated diagnostics that were developed for and that are implemented in the IBM 3081 Processor Complex are presented in this paper. Significant features of the 3081 diagnostics methodology are the capability to isolate intermittent as well as solid hardware failures, and the automatic isolation of a failure to the failing field-replaceable unit (FRU) in a high percentage of the cases. These features, which permit a considerable reduction in the time to repair a failure as compared to previous systems, are achieved by designing a machine which has a very high level of error-detection capability as well as special functions to facilitate fault isolation using Level-Sensitive Scan Design (USD), and which includes a Processor Controller to implement diagnostic microprograms. Intermittent failures are isolated by analyzing data captured at the detection of the error, and the analysis is concurrent with customer operations if the error is recoverable. A further improvement in the degree of isolation is achieved for solid failures by using automatically generated validation tests which detect and isolate stuck faults in the logic. The diagnostic package was designed to meet a specified value of isolation effectiveness, stated as the average number of FRUs replaced per failure. The technique used to estimate the isolation effectiveness of the diagnostic package and to evaluate proposals for improving isolation is described. Testing of the diagnostic package by hardware bugging indicates very good correlation between projected and measured effectiveness.

Nandakurnar N. Tendolkar

Papers

Automated diagnostic methodology for the IBM 3081 processor complex