Showing papers by "Narain D. Arora published in 2002"
07 Aug 2002
TL;DR: In this paper, a quasi-3D capacitance model based on an effective width (W/sub eff/) concept was proposed for capacitance extraction from a 2D model combined with a 3D "wall-to-wall" approach.
Abstract: We propose a novel quasi-3D capacitance model based on an "effective width" (W/sub eff/) concept. The model is derived from a new analytical 2D model combined with a 3D "wall-to-wall" approach. With W/sub eff/, complicated 3D structures are readily interpreted as a combination of consecutive 2D structures, leading to efficient capacitance extraction. The analytical 2D model is generated for easy application to recent technology, featuring multilayer dielectric and non-ideal vertical profile. Finally, our model is generalized to diagonal routing and confirmed by comparison with a field solver.
16 citations
08 Dec 2002
TL;DR: In this article, the authors proposed a first-ever analytic inductance model for practical on-chip interconnects with random signal lines, and verified the effectiveness of the effective loop inductance approach and determination of return paths through random capacitive coupling using a full-wave solver.
Abstract: We propose a first-ever analytic inductance model for practical on-chip interconnects with random signal lines. Validity of the effective loop inductance approach and determination of return paths through random capacitive coupling are investigated using a full-wave solver, leading to a frequency-dependent RLC model. Non-orthogonal interconnects are also investigated and included in our model.
9 citations