A method to determine the small-signal equivalent circuit of FETs is proposed This method consists of a direct determination of both the extrinsic and intrinsic small-signal parameters in a low-frequency band This method is fast and accurate, and the determined equivalent circuit fits the S-parameters well up to 265 GHz >

A new method for determining the FET small-signal equivalent circuit

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20I%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

/pdf/mos2-transistors-with-1-nanometer-gate-lengths-389j9ig3a6.pdf

MoS2 transistors with 1-nanometer gate lengths

This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance.

http://iulian.lmn.pub.ro/wiki_iulian/bibliografie/2000_Yue200_ED.pdf

Physical modeling of spiral inductors on silicon

Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/'' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.

Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors

Semiconductor Device Modeling For VLSI

A model describing C-V and I-V characteristics of modulation doped FET's is proposed. The model takes into account the change in the Fermi energy with the gate voltage. At high two dimensional electron concentrations, the equations of the model for the charge control by the gate voltage become similar to the equations of the charge control model where the thickness d of AlGaAs layer should be substituted by d + Δ d and Δ d is the effective width of the potential well (≃ 80 A). Another important prediction of the model is the existence of the "subthreshold" current. A very good quantitative agreement is obtained with our experimental I-V curves using the measured values of the low field mobility and the source resistance.

Model for modulation doped field effect transistor

An experimental 2.4-GHz CMOS radio composed of RF and digital circuits for the low-power and low-rate preliminary IEEE802.15.4 WPAN is reported, consuming 21 mW in receive mode and 30 mW in transmit mode. The RF design focus is to maximize linearity for a given power consumption using linearization methods which lead an order of magnitude improvement in LNA/mixer IIP3/power performance. Chip-on-PCB technology allows implementation of a coin-sized radio at very low cost, which also provides 3 dBi gain patch antenna and high Q (>50) inductors.

An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz

A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit. The cell delay of the ring oscillator is smaller than a fundamental inverter delay. Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.

Kwyro Lee

Papers

Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors

Semiconductor Device Modeling For VLSI

Model for modulation doped field effect transistor

An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz

A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme