Nazanin Calagar

TL;DR: A source-level debugging framework for FPGA high-level synthesis (HLS) that offers gdb-like step, break, and data inspection functionality for an HLS-generated hardware circuit and permits concurrent hardware and software debugging to discover the first point at which any logic signal in the hardware mismatches with its corresponding variable in software.

TL;DR: This paper presents on overview of the LegUp design methodology and system architecture, and discusses ongoing work on profiling, hardware/software partitioning, hardware accelerator quality improvements, Pthreads/OpenMP support, visualization tools, and debugging support.

TL;DR: This work presents a new HLS-directed approach to compiler optimizations, wherein it executes partial HLS and profiling at intermittent points in the optimization process and uses the results to judiciously undo the impact of optimization passes predicted to be damaging to the generated hardware quality.

TL;DR: The LegUp framework is overviewed and support for an embedded ARM processor, as is available on Altera's recently released SoC FPGA, HLS support for software parallelization schemes -- pthreads and OpenMP, and a preliminary debugging and verification framework providing C source-level debugging of HLS hardware are described.

TL;DR: This work applies high-level synthesis (HLS) to generate Blokus Duo game-playing hardware for the FPT 2013 Design Competition, and includes a custom stack implementation that uses only integer arithmetic, and employs the use of bitwise logical operations to improve overall computational performance.