Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. >

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Low-power CMOS digital design

We introduce the notion of a Physical Random Function (PUF). We argue that a complex integrated circuit can be viewed as a silicon PUF and describe a technique to identify and authenticate individual integrated circuits (ICs).We describe several possible circuit realizations of different PUFs. These circuits have been implemented in commodity Field Programmable Gate Arrays (FPGAs). We present experiments which indicate that reliable authentication of individual FPGAs can be performed even in the presence of significant environmental variations.We describe how secure smart cards can be built, and also briefly describe how PUFs can be applied to licensing and certification applications.

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Silicon physical random functions

This paper presents experimental measurements of the differences between a 90-nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and, thereby, improve FPGAs. We describe the methodology by which the measurements were obtained and show that, for circuits containing only look-up table-based logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 35. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories. We find that these blocks reduce this average area gap significantly to as little as 18 for our benchmarks, and we estimate that extensive use of these hard blocks could potentially lower the gap to below five. The ratio of critical-path delay, from FPGA to ASIC, is roughly three to four with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 14 times and, with hard blocks, this gap generally becomes smaller

Measuring the Gap Between FPGAs and ASICs

An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

/pdf/minimizing-power-consumption-in-digital-cmos-circuits-2ibdk90up4.pdf

Minimizing power consumption in digital CMOS circuits

Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such as smartcards and ATMs. Arbiter-based physical unclonable functions (PUFs) exploit the statistical delay variation of wires and transistors across integrated circuits (ICs) in manufacturing processes to build unclonable secret keys. We fabricated arbiter-based PUFs in custom silicon and investigated the identification capability, reliability, and security of this scheme. Experimental results and theoretical studies show that a sufficient amount of inter-chip variation exists to enable each IC to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage. We show that arbiter-based PUFs are realizable and well suited to build, for example, key-cards that need to be resistant to physical attacks.

Extracting secret keys from integrated circuits

A 500 MHz op-amp-RC filter in a 0.18 /spl mu/m CMOS process achieves an integrator signal swing of 1.73 V/sub pp/ for -40 dB THD and thermal noise of 18 nV//spl radic/Hz. A three-stage op-amp with two feed-forward paths and common-mode feedback local to each stage is used. The op-amp features 8 GHz unity-gain frequency and 40 dB gain at 500 MHz.

A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedback

A monolithic radio integrated circuit includes a substrate, a set of one or more analog subcircuits on the substrate, a programmable bias current supply on the substrate coupled to the set to provide bias currents to the analog subcircuits of the set including programmable bias currents to one or more analog subcircuits forming a first subset of the set, and a digital subsection coupled to the programmable bias supply to determine the bias currents supplied to the analog subcircuits of the first subset, such that one or more characteristics of the radio integrated circuit are modifiable by programming the programmable bias supply.

CMOS wireless transceiver with programmable characteristics

TOPOLOGIZER is an expert system for the design of CMOS cells. It automatically generates a symbolic layout given a transistor connection list and a description of the boundary assignment of external cell connections. As part of an overall approach to silicon compilation it uses expert designer specified heuristics to perform the difficult task of converting a structural description (schematic) into a physical description that maintains some notion of structured layout principles.

TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout

Known signal processors for matching signal patterns commonly compare an unknown signal with one of a set of reference signals Various comparison techniques are known One comparison technique for solving a parenthesization problem includes an orthogonal array of interconnected cells which are adapted for dynamic programming and for extending data and control information in a generally left-to-right direction as well as in a bottom-to-top direction For solving a pattern matching problem, known arrangements for extending control information in a generally left-to-right or bottom-to-top direction do not appear to be satisfactory The disclosed signal processor for matching signal patterns and for dynamically time warping an unknown input signal with a reference input signal generates a measure of the correspondence between the input signals In generating the correspondence measure, the processor includes an arrangement for controlling all processor cells on a predetermined diagonal of the array of cells Thereby all cells coupled to the diagonal can operate in parallel to increase and improve the efficiency of the signal processor The processor also includes an arrangement for controlling all processor cells on each diagonal of the array of cells As a result, not only can all cells on each diagonal operate in parallel but also each of the plurality of diagonals can operate in parallel for processing the same or different sets of input signals Thereby, a still further increase in the efficiency of the signal processor obtains

Time warp signal recognition processor for matching signal patterns

To overcome the bandwidth limitation of a random access memory (RAM), a shift register (20) is disposed within the memory array (1) such that the shift register lies parallel to the row lines and is connected to at least one of the bit lines contained within the array. Separate high-speed serial input and output lines (21, 22) are provided by the shift register. These lines are in addition to and operate independently of the slower speed input and output lines normally provided by the RAM. Through this arrangement, a row of data can be transferred to and from the memory array at a rate substantially faster than the single-bit access rate of the RAM.

Neil Weste

Papers

A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedback

CMOS wireless transceiver with programmable characteristics

TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout

Time warp signal recognition processor for matching signal patterns

Random access memory system having high-speed serial data paths