To reduce the high test time for serial scan designs, the use of multiple scan chains has been proposed. In this paper we consider the problem of optimally constructing multiple scan chains so as to minimize ovemll test time. Rather than follow the tmditional practice of using equal length chains, we allow the chains to be of different lengths, and show that this can lead to lower test times. The main idea in our approach is to assign those scan elements that are more frequently accessed to shorter scan chains. Given a design with N scan elements, and given that k scan chains are to be used for a pl in tests, we present an algorithm of complezity O(kN ) for configuring the chains such that the overall test application time is minimized. By analyzing a range of circuit topologies, we demonstrate test time reductions as large as 40% over equal length chain conjigurations. cyg

Configuring multiple scan chains for minimum test time

This paper describes the architecture of a bit-serial VLSI circuit designed for digital signal processing applications. This circuit is capable of performing matrix-vector multiplications in a totally pipeline fashion. Although this circuit naturally performs multiplication of a 3 \times 3 matrix with a 3-element vector at a time, it can perform a (matrix) \times (vector) operation of any size. Under different control modes, the same architecture can also perform vector addition and scalar multiplication of vectors of arbitrary length. The circuit has been designed for a single chip implementation using 4 \mu -NMOS technology. The word size of the chip is 16 bits, and the data is provided in 2's complement form. The chip contains approximately 6000 transistors in an area of 5.7 {mm}^{2} and operates with a 6-MHz two-phase clock in direct interface with a 6-MHz microprocessor. It can also be interfaced with a programmable digital signal processor. The chip is housed in a 64-pin DIP. A self-testing scheme incorporated into the design allows fault detection and isolation in a particular unit (storage or arithmetic unit) during the data processing.

A bit-serial architecture for digital signal processing

In order to protect the data during system crash, traditional DRAM–DISK architecture file systems (e.g., EXT4) need to synchronize the dirty metadata and data from the memory to disk. At the same time, the disk synchronization may break the consistency of file system upon a crash, so traditional file systems use some mechanisms to guarantee the file system consistency when the dirty metadata and data is synchronized onto persistent storage devices (e.g., HDD and SSD). Journaling is a consistency mechanism widely used by file systems. We observe that the overhead of periodic disk synchronization and journaling is high. Emerging non-volatile memories (NVMs) can be potentially utilized to reduce these overheads. In this paper, we present hybrid architecture for storage file system (HasFS), a file system designed for the DRAM–NVM–DISK architecture. HasFS extends the main memory with NVM and considers NVM as a persistent page cache to eliminate the periodic disk synchronization overhead of dirty data. Then we design an efficient consistency mechanism based on the hybrid memory architecture to provide strong (both metadata and data) consistency guarantee with low overhead. The evaluation demonstrates that HasFS outperforms mainstream DRAM–DISK file systems for many workloads. For instance, HasFS has between 1.6X to 46.6X performance improvement over other tested file systems in random write workload. In particular, HasFS outperforms EXT4 without journal in some cases even though HasFS provides metadata and data consistency guarantees (similar to EXT4 with journal data mode).

HasFS: optimizing file system consistency mechanism on NVM-based hybrid storage architecture

This paper discusses design for testability automation within a silicon compiler environment under development at GTE Laboratories Inc. The proposed rule-based modular design for testability methodology utilizes both BIST and scan path techniques for full custom VLSI designs. An on-chip test controller may be used. Testability evaluation is performed using both controllability/observability and information theoretic methods. A testability "expert" is required which can manage the analysis as it evolves during the synthesis process and which can make the ultimate testability decisions. Problems involved with integrating the approach with an emerging silicon compilation system are discussed.

Design for Testability in a Silicon Compilation Environment

Today's computing architectures suffer from the three well-known bottlenecks, which are the memory, the power and the instruction-level parallelism walls. Emerging non-volatile technologies, such as memristor, enable new resistive architectures that alleviate at least two of such bottlenecks, as they can process data within the memory with almost no leakage. In this paper, we propose a novel resistive computing architecture by extending a conventional architecture with a resistive based Computation-In-Memory accelerator (CIMX). We evaluate the delay, energy and area of the conventional and CIMX architecture using an analytical model and a simulation framework. The results (both based on the analytical model and simulation framework) show that the proposed architecture achieves at least one order of magnitude improvement in terms of performance, area, and energy efficiency for the considered benchmarks.

A computation-in-memory accelerator based on resistive devices

This article presents design for testability and self-testing approaches for bit-serial signal processors?specifically, for an integrated circuit consisting of bit-serial data paths whose integration level requires approximately 120,000 transistors packaged in a 68-pin chip carrier. The bit-serial architecture lends itself to a scan-type approach for functional testing with minimum design modification. The functional verification testing requires less than one percent additional hardware, plus a minimum of four additional I/O package pins. Although less straightforward, self-testing was still accomplished without execessive penalties. A potential solution to the problem of data integrity of the interchip communication lines required only a minimum amount of hardware and additional I/O pins.

Nikos Kanopoulos

Papers

Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors