N
Ning Wu
Researcher at Intel
Publications - 6
Citations - 423
Ning Wu is an academic researcher from Intel. The author has contributed to research in topics: Memory management & Memory map. The author has an hindex of 4, co-authored 6 publications receiving 406 citations.
Papers
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Proceedings ArticleDOI
Bit error rate in NAND Flash memories
Neal R. Mielke,Todd A. Marquart,Ning Wu,Jeffrey Alan Kessenich,Hanmant P. Belgal,Eric Schares,F. Trivedi,E. Goodness,L.R. Nevill +8 more
TL;DR: NAND flash memories have bit errors that are corrected by error-correction codes (ECC), but UBER is a strong function of program/erase cycling and subsequent retention time, so UBER specifications must be coupled with maximum specifications for these quantities.
Patent
Apparatus, system, and method for improving read endurance for a non-volatile memory
TL;DR: In this article, an apparatus, system, and method for improving read endurance for a nonvolatile memory (NVM) is described, which comprises: determining a read count corresponding to a block of NVM; identifying whether the block is a partially programmed block (PPB); and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold.
Patent
Data recovery in memory devices
TL;DR: In this article, a memory controller can be configured to detect corrupted data in a selected data region in the first non-volatile memory, which can be associated with an increased risk of data corruption after data is written from the second NVM to the first NVM.
Patent
Configuration information backup in memory systems
TL;DR: In this paper, the authors present a configuration manager that includes status detection logic, retrieval logic, and configuration management logic, which are used to initialize a first memory device to be initialized with custom configuration settings stored in the second memory device.
Patent
Managing redundancy information in a non-volatile memory
TL;DR: In this article, a memory controller includes memory allocation logic to organize memory resources of individual memory dice of a memory device into a plurality of virtual dice, including a redundancy virtual die for storing redundancy information and a data virtual dice for storing data, and redundancy information logic to generate redundancy information based on the data and to write the redundancy information to the virtual die of the non-volatile memory device.