Network Optimization: Continuous and Discrete Models

A packet transmitting apparatus ( 401 ) capable of transmitting a copyright-protected content across an IP network includes: a transmission condition setting/managing unit ( 403 ) that extracts from inputted non-A/V data or A/V data at least one information of billing information, reproduction control information, copy control information for the A/V data, and packet output control information, and generate encryption mode information indicating an encryption mode which becomes a condition during transmission of the A/V data; an encrypted data generation unit ( 422 ) that encrypts inputted A/V data based on a transmission condition determined by combining input terminal information, data format information, and attribute information, and adds an encryption information header based on the encryption mode information and time-based discontinuity information to the encrypted A/V data so as to generate encrypted data; and a packetization unit ( 406 ) that generates a packet by adding a packet header and information representing a time-based discontinuity point to the generated encryption data.

Packet transmitting apparatus

A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Data transfer control device and electronic instrument

In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.

Providing Integrity Verification And Attestation In A Hidden Execution Environment

The Degree Constrained Minimum Spanning Tree (DCMST) on a graph is the problem of generating a minimum spanning tree with constraints on the number of arcs that can be incident to vertices of the graph. In this paper we develop three heuristics for the DCMST, including simulated annealing, a genetic algorithm and a method based on problem space search. We propose alternative tree representations to facilitate the neighbourhood searches for the genetic algorithm. The tree representation that we use for the genetic algorithm can be generalised to other tree optimisation problems as well. We compare the computational performance of all of these approaches against the performance of an exact solution approach in the literature. In addition, we also develop a new exact solution approach based on the combinatorial structure of the problem. We test all of these approaches using standard problems taken from the literature and some new test problems that we generate.

Comparison of Algorithms for the Degree Constrained Minimum Spanning Tree

The minimum spanning tree problem with an added constraint that no node in the spanning tree has the degree more than a specified integer, d, is known as the minimum-weight degree-constrained spanning tree (d-MST) problem. Such a constraint arises, for example, in VLSI routing trees, in backplane wiring, or in minimizing single-point failures for communication networks. The d-MST problem is NP-complete. Here, we develop four heuristics for approximate solutions to the problem and implement them on a massivelyparallel SIMD machine, MasPar MP-1. An extensive empirical study shows that for random graphs on up to 5000 nodes (about 12.5 million edges), the heuristics produce solutions close to the optimal in less than 10 seconds. The heuristics were also tested on a number of TSP benchmark problems to compute spanning trees with a degree bound d = 3.

Minimum-weight degree-constrained spanning tree problem: heuristics and implementation on an SIMD parallel machine

Computing spanning trees with specific properties and constraints lies at the heart of many real-life network optimization problems. Here, a compilation of 29 constrained spanning tree problems is presented. Since most of these problems are NP-complete, good approximate heuristics are needed to solve them on parallel machines. We develop two generic methods for handling large graphs on massively-parallel SIMD machines.

Computation of Constrained Spanning Trees: A Unified Approach

A system-on-a-chip (SoC) to process digital audio-video content includes one or more input/output (I/O) interfaces to transmit the digital audio-video content to corresponding I/O devices coupled to the SoC and to receive the digital audio-video content from the corresponding I/O devices. The SoC also includes a cryptographic engine to encrypt the digital audio-video content being transmitted via the I/O interfaces to the corresponding I/O devices and to decrypt the digital audio-video content received via the I/O interfaces from the corresponding I/O devices.

Integrated encryption/decryption functionality in a digital TV/PVR system-on-chip

A transport processor that can be used in a digital audio-video receiver system comprises a front end and a memory interface. The front end receives concurrently a plurality of transport streams, where two or more of the plurality of transport streams can have different formats, and each transport stream includes a plurality of packets. The front end includes a packet processor to create an aggregate transport stream in a single format from the plurality of transport streams. The memory interface is an interface through which the transport processor can store the aggregate transport stream in a memory for use by subsequent decode and display operations.

Flexible and scalable architecture for transport processing

The invention provides techniques to implement unique identifier for an integrated chip and how this ID can be employed to enhance the security of content in personal video recorder type systems. The storage device can be a hard disk, a removable storage medium or any other type of storage medium. An integrated circuit (IC) within the personal video recorder stores a unique identifier that is used in for encryption and decryption of data stored on the storage device. Several embodiments are disclosed herein that maintain the secrecy of the unique ID such that it is not easily accessible thereby defeating the security scheme.

Nishit Kumar

Papers

Minimum-weight degree-constrained spanning tree problem: heuristics and implementation on an SIMD parallel machine

Computation of Constrained Spanning Trees: A Unified Approach

Integrated encryption/decryption functionality in a digital TV/PVR system-on-chip

Flexible and scalable architecture for transport processing

Unique identifier per chip for digital audio/video data encryption/decryption in personal video recorders