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Norbert Juffa
Researcher at Advanced Micro Devices
Publications - 22
Citations - 668
Norbert Juffa is an academic researcher from Advanced Micro Devices. The author has contributed to research in topics: Multiplier (economics) & Operand. The author has an hindex of 15, co-authored 22 publications receiving 668 citations.
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Patent
Converting register data from a first format type to a second format type if a second type instruction consumes data produced by a first type instruction
TL;DR: In this article, a microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats: the floating point data format and the multimedia data format.
Patent
Method and apparatus for multi-function arithmetic
TL;DR: In this paper, a multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed, where the multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form.
Patent
Floating point addition pipeline including extreme value, comparison and accumulate functions
TL;DR: In this paper, a multimedia execution unit is configured to perform vectored floating point and integer instructions, including an add/subtract pipeline having far and close data paths, where the far path handles effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one.
Patent
Method and apparatus for achieving higher frequencies of exactly rounded results
TL;DR: In this article, a multiplier configured to obtain higher frequencies of exactly rounded results by adding an adjustment constant to intermediate products generated during iterative multiplication operations is disclosed, and the results converge toward an infinitely precise result.
Patent
Method and apparatus for rounding in a multiplier arithmetic
TL;DR: In this article, a multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed, where the multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form.