The Tofu interconnect uses a 6D mesh/torus topology in which each cubic fragment of the network has the embeddability of a 3D torus graph, allowing users to run multiple topology-aware applications. This article describes the Tofu interconnect architecture, the Tofu network router, the Tofu network interface, and the Tofu barrier interface, and presents preliminary evaluation results.

The Tofu Interconnect

The K computer is a distributed memory supercomputer system consisting of more than 80,000 compute nodes which is being developed by RIKEN as a Japanese national project. Its performance is aimed at achieving 10 peta-flops sustained in the LINPACK benchmark. The system is under installation and adjustment. The whole system will be operational in 2012.

The K computer: Japanese next-generation supercomputer development project

Augmenting a processor with special hardware that is able to apply a Single Instruction to Multiple Data(SIMD) at the same time is a cost effective way of improving processor performance. It also offers a means of improving the ratio of processor performance to power usage due to reduced and more effective data movement and intrinsically lower instruction counts. This paper considers and compares the NEON SIMD instruction set used on the ARM Cortex-A series of RISC processors with the SSE2 SIMD instruction set found on Intel platforms within the context of the Open Computer Vision (OpenCV) library. The performance obtained using compiler auto-vectorization is compared with that achieved using hand-tuning across a range of five different benchmarks and ten different hardware platforms. On the ARM platforms the hand-tuned NEON benchmarks were between 1.05× and 13.88× faster than the auto-vectorized code, while for the Intel platforms the hand-tuned SSE benchmarks were between 1.34× and 5.54× faster.

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Use of SIMD Vector Operations to Accelerate Application Code Performance on Low-Powered ARM and Intel Platforms

In this report we give an overview of parallel- and vector computers which are currently available or will become available within a short time frame from vendors; no attempt is made to list all machines that are still in the research phase. The machines are described according to their architectural class. Shared- and distributed memory SIMD- and MIMD machines are discerned. The information about each machine is kept as compact as possible. Moreover, no attempt is made to quote prices as these are often even more elusive than the performance of a system. This document reflects the technical state of the supercomuter arena as accurately as possible. However, the authors nor their employers take any responsibility for errors or mistakes in this document. We encourage anyone who has comments or remarks on the contents to inform us, so we can improve this work.

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Overview of Recent Supercomputers

Real space DFT (RSDFT) is a simulation technique most suitable for massively-parallel architectures to perform first-principles electronic-structure calculations based on density functional theory. We here report unprecedented simulations on the electron states of silicon nanowires with up to 107,292 atoms carried out during the initial performance evaluation phase of the K computer being developed at RIKEN. The RSDFT code has been parallelized and optimized so as to make effective use of the various capabilities of the K computer. Simulation results for the self-consistent electron states of a silicon nanowire with 10,000 atoms were obtained in a run lasting about 24 hours and using 6,144 cores of the K computer. A 3.08 peta-flops sustained performance was measured for one iteration of the SCF calculation in a 107,292-atom Si nanowire calculation using 442,368 cores, which is 43.63% of the peak performance of 7.07 peta-flops.

First-principles calculations of electron states of a silicon nanowire with 100,000 atoms on the K computer

The Sparc64 VIIIfx eight-core processor, developed for use in petascale computing systems, runs at speeds of up to 2 GHz and achieves a peak performance of 128 gigaflops while consuming as little as 58 watts of power. Sparc64 VIIIfx realizes a six-fold improvement in performance per watt over previous generation Sparc64 processors.

Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing

A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.

Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method

A signal restoration circuit includes storage (4) and a storage controller (6). The storage (4) is configured to store input signals by disposing the input signals in an input order and the input signals are readable from the storage in the disposed order. The storage controller (6) is configured to control delay time from an input of the input signal to an output in the storage (4) based on delay information of the input signal. When a delay amount of the input signal is large, the delay time is reduced, and when the delay amount of the input signal is small, the delay time is increased.

Signal decoding circuit, latency adjustment circuit, memory controller, processor, computer, signal decoding method, and latency adjustment method

A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through #5. Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.

Memory control device and method for controlling same

A priority control register 104 dynamically controls the internal transition state based on the issuability state of a memory request obtained in the memory request issuability signal generation unit 106 and retaining state of the memory request in the REQ_BUF 102 obtained by each of determination circuits 105 #2 through # 5 . Thus, the jump control of the priorities corresponding to the access regulation of the DRAM module 109 can be realized.

Noriyuki Takahashi

Papers

Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing

Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method

Signal decoding circuit, latency adjustment circuit, memory controller, processor, computer, signal decoding method, and latency adjustment method

Memory control device and method for controlling same

Memory control device and method